Merge pull request #3290 from mpasternacki/bugfix/freebsd-build

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 7a83d28e7d3678ecc8205adea6fb03f9a7672463..642eb42b25d0f7d0692865f9a3e49e40a8f230ac 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -91,10 +91,10 @@ struct ConstEval
        {
                if (cell->type == ID($lcu))
                {
-                       RTLIL::SigSpec sig_p = cell->getPort(ID(P));
-                       RTLIL::SigSpec sig_g = cell->getPort(ID(G));
-                       RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
-                       RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO))));
+                       RTLIL::SigSpec sig_p = cell->getPort(ID::P);
+                       RTLIL::SigSpec sig_g = cell->getPort(ID::G);
+                       RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+                       RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
 
                        if (sig_co.is_fully_const())
                                return true;
@@ -133,10 +133,8 @@ struct ConstEval
                if (sig_y.is_fully_const())
                        return true;
 
-               if (cell->hasPort(ID(S))) {
-                       sig_s = cell->getPort(ID(S));
-                       if (!eval(sig_s, undef, cell))
-                               return false;
+               if (cell->hasPort(ID::S)) {
+                       sig_s = cell->getPort(ID::S);
                }
 
                if (cell->hasPort(ID::A))
@@ -151,6 +149,9 @@ struct ConstEval
                        int count_maybe_set_s_bits = 0;
                        int count_set_s_bits = 0;
 
+                       if (!eval(sig_s, undef, cell))
+                               return false;
+
                        for (int i = 0; i < sig_s.size(); i++)
                        {
                                RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
@@ -198,10 +199,40 @@ struct ConstEval
                        else
                                set(sig_y, y_values.front());
                }
+               else if (cell->type == ID($bmux))
+               {
+                       if (!eval(sig_s, undef, cell))
+                               return false;
+
+                       if (sig_s.is_fully_def()) {
+                               int sel = sig_s.as_int();
+                               int width = GetSize(sig_y);
+                               SigSpec res = sig_a.extract(sel * width, width);
+                               if (!eval(res, undef, cell))
+                                       return false;
+                               set(sig_y, res.as_const());
+                       } else {
+                               if (!eval(sig_a, undef, cell))
+                                       return false;
+                               set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
+                       }
+               }
+               else if (cell->type == ID($demux))
+               {
+                       if (!eval(sig_a, undef, cell))
+                               return false;
+                       if (sig_a.is_fully_zero()) {
+                               set(sig_y, Const(0, GetSize(sig_y)));
+                       } else {
+                               if (!eval(sig_s, undef, cell))
+                                       return false;
+                               set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
+                       }
+               }
                else if (cell->type == ID($fa))
                {
-                       RTLIL::SigSpec sig_c = cell->getPort(ID(C));
-                       RTLIL::SigSpec sig_x = cell->getPort(ID(X));
+                       RTLIL::SigSpec sig_c = cell->getPort(ID::C);
+                       RTLIL::SigSpec sig_x = cell->getPort(ID::X);
                        int width = GetSize(sig_c);
 
                        if (!eval(sig_a, undef, cell))
@@ -229,11 +260,11 @@ struct ConstEval
                }
                else if (cell->type == ID($alu))
                {
-                       bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool();
-                       bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool();
+                       bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
+                       bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
 
-                       RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
-                       RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
+                       RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+                       RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
 
                        if (!eval(sig_a, undef, cell))
                                return false;
@@ -247,8 +278,8 @@ struct ConstEval
                        if (!eval(sig_bi, undef, cell))
                                return false;
 
-                       RTLIL::SigSpec sig_x = cell->getPort(ID(X));
-                       RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
+                       RTLIL::SigSpec sig_x = cell->getPort(ID::X);
+                       RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
 
                        bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
                        sig_a.extend_u0(GetSize(sig_y), signed_a);
@@ -309,10 +340,10 @@ struct ConstEval
                        RTLIL::SigSpec sig_c, sig_d;
 
                        if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
-                               if (cell->hasPort(ID(C)))
-                                       sig_c = cell->getPort(ID(C));
-                               if (cell->hasPort(ID(D)))
-                                       sig_d = cell->getPort(ID(D));
+                               if (cell->hasPort(ID::C))
+                                       sig_c = cell->getPort(ID::C);
+                               if (cell->hasPort(ID::D))
+                                       sig_d = cell->getPort(ID::D);
                        }
 
                        if (sig_a.size() > 0 && !eval(sig_a, undef, cell))