Merge pull request #3290 from mpasternacki/bugfix/freebsd-build

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index ff8cf86d62bb0f282fa37db6a918ef5aa30adec1..642eb42b25d0f7d0692865f9a3e49e40a8f230ac 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -135,8 +135,6 @@ struct ConstEval
 
                if (cell->hasPort(ID::S)) {
                        sig_s = cell->getPort(ID::S);
-                       if (!eval(sig_s, undef, cell))
-                               return false;
                }
 
                if (cell->hasPort(ID::A))
@@ -151,6 +149,9 @@ struct ConstEval
                        int count_maybe_set_s_bits = 0;
                        int count_set_s_bits = 0;
 
+                       if (!eval(sig_s, undef, cell))
+                               return false;
+
                        for (int i = 0; i < sig_s.size(); i++)
                        {
                                RTLIL::State s_bit = sig_s.extract(i, 1).as_const().bits.at(0);
@@ -198,6 +199,36 @@ struct ConstEval
                        else
                                set(sig_y, y_values.front());
                }
+               else if (cell->type == ID($bmux))
+               {
+                       if (!eval(sig_s, undef, cell))
+                               return false;
+
+                       if (sig_s.is_fully_def()) {
+                               int sel = sig_s.as_int();
+                               int width = GetSize(sig_y);
+                               SigSpec res = sig_a.extract(sel * width, width);
+                               if (!eval(res, undef, cell))
+                                       return false;
+                               set(sig_y, res.as_const());
+                       } else {
+                               if (!eval(sig_a, undef, cell))
+                                       return false;
+                               set(sig_y, const_bmux(sig_a.as_const(), sig_s.as_const()));
+                       }
+               }
+               else if (cell->type == ID($demux))
+               {
+                       if (!eval(sig_a, undef, cell))
+                               return false;
+                       if (sig_a.is_fully_zero()) {
+                               set(sig_y, Const(0, GetSize(sig_y)));
+                       } else {
+                               if (!eval(sig_s, undef, cell))
+                                       return false;
+                               set(sig_y, const_demux(sig_a.as_const(), sig_s.as_const()));
+                       }
+               }
                else if (cell->type == ID($fa))
                {
                        RTLIL::SigSpec sig_c = cell->getPort(ID::C);