Added $lcu cell type

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index d42c2b0f138b04c7aec78722342ffdfb57861332..6e507bd515df3a0212bddd22b22139deff47281e 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -23,6 +23,7 @@
 #include "kernel/rtlil.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
+#include "kernel/macc.h"
 
 struct ConstEval
 {
@@ -85,6 +86,43 @@ struct ConstEval
 
        bool eval(RTLIL::Cell *cell, RTLIL::SigSpec &undef)
        {
+               if (cell->type == "$lcu")
+               {
+                       RTLIL::SigSpec sig_p = cell->getPort("\\P");
+                       RTLIL::SigSpec sig_g = cell->getPort("\\G");
+                       RTLIL::SigSpec sig_ci = cell->getPort("\\CI");
+                       RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort("\\CO")));
+
+                       if (sig_co.is_fully_const())
+                               return true;
+
+                       if (!eval(sig_p, undef, cell))
+                               return false;
+
+                       if (!eval(sig_g, undef, cell))
+                               return false;
+
+                       if (!eval(sig_ci, undef, cell))
+                               return false;
+
+                       if (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())
+                       {
+                               RTLIL::Const coval(RTLIL::Sx, SIZE(sig_co));
+                               bool carry = sig_ci.as_bool();
+
+                               for (int i = 0; i < SIZE(coval); i++) {
+                                       carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry);
+                                       coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0;
+                               }
+
+                               set(sig_co, coval);
+                       }
+                       else
+                               set(sig_co, RTLIL::Const(RTLIL::Sx, SIZE(sig_co)));
+
+                       return true;
+               }
+
                RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
                log_assert(cell->hasPort("\\Y"));
@@ -154,6 +192,108 @@ struct ConstEval
                        else
                                set(sig_y, y_values.front());
                }
+               else if (cell->type == "$fa")
+               {
+                       RTLIL::SigSpec sig_c = cell->getPort("\\C");
+                       RTLIL::SigSpec sig_x = cell->getPort("\\X");
+                       int width = SIZE(sig_c);
+
+                       if (!eval(sig_a, undef, cell))
+                               return false;
+
+                       if (!eval(sig_b, undef, cell))
+                               return false;
+
+                       if (!eval(sig_c, undef, cell))
+                               return false;
+
+                       RTLIL::Const t1 = const_xor(sig_a.as_const(), sig_b.as_const(), false, false, width);
+                       RTLIL::Const val_y = const_xor(t1, sig_c.as_const(), false, false, width);
+
+                       RTLIL::Const t2 = const_and(sig_a.as_const(), sig_b.as_const(), false, false, width);
+                       RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
+                       RTLIL::Const val_x = const_or(t2, t3, false, false, width);
+
+                       set(sig_y, val_y);
+                       set(sig_x, val_x);
+               }
+               else if (cell->type == "$alu")
+               {
+                       bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
+                       bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
+
+                       RTLIL::SigSpec sig_ci = cell->getPort("\\CI");
+                       RTLIL::SigSpec sig_bi = cell->getPort("\\BI");
+
+                       if (!eval(sig_a, undef, cell))
+                               return false;
+
+                       if (!eval(sig_b, undef, cell))
+                               return false;
+
+                       if (!eval(sig_ci, undef, cell))
+                               return false;
+
+                       if (!eval(sig_bi, undef, cell))
+                               return false;
+
+                       RTLIL::SigSpec sig_x = cell->getPort("\\X");
+                       RTLIL::SigSpec sig_co = cell->getPort("\\CO");
+
+                       bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
+                       sig_a.extend_u0(SIZE(sig_y), signed_a);
+                       sig_b.extend_u0(SIZE(sig_y), signed_b);
+
+                       bool carry = sig_ci[0] == RTLIL::S1;
+                       bool b_inv = sig_bi[0] == RTLIL::S1;
+
+                       for (int i = 0; i < SIZE(sig_y); i++)
+                       {
+                               RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };
+
+                               if (!x_inputs.is_fully_def()) {
+                                       set(sig_x[i], RTLIL::Sx);
+                               } else {
+                                       bool bit_a = sig_a[i] == RTLIL::S1;
+                                       bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+                                       bool bit_x = bit_a != bit_b;
+                                       set(sig_x[i], bit_x ? RTLIL::S1 : RTLIL::S0);
+                               }
+
+                               if (any_input_undef) {
+                                       set(sig_y[i], RTLIL::Sx);
+                                       set(sig_co[i], RTLIL::Sx);
+                               } else {
+                                       bool bit_a = sig_a[i] == RTLIL::S1;
+                                       bool bit_b = (sig_b[i] == RTLIL::S1) != b_inv;
+                                       bool bit_y = (bit_a != bit_b) != carry;
+                                       carry = (bit_a && bit_b) || (bit_a && carry) || (bit_b && carry);
+                                       set(sig_y[i], bit_y ? RTLIL::S1 : RTLIL::S0);
+                                       set(sig_co[i], carry ? RTLIL::S1 : RTLIL::S0);
+                               }
+                       }
+               }
+               else if (cell->type == "$macc")
+               {
+                       Macc macc;
+                       macc.from_cell(cell);
+
+                       if (!eval(macc.bit_ports, undef, cell))
+                               return false;
+
+                       for (auto &port : macc.ports) {
+                               if (!eval(port.in_a, undef, cell))
+                                       return false;
+                               if (!eval(port.in_b, undef, cell))
+                                       return false;
+                       }
+
+                       RTLIL::Const result(0, SIZE(cell->getPort("\\Y")));
+                       if (!macc.eval(result))
+                               log_abort();
+
+                       set(cell->getPort("\\Y"), result);
+               }
                else
                {
                        RTLIL::SigSpec sig_c, sig_d;