Merge pull request #1814 from YosysHQ/mmicko/pyosys_makefile

[yosys.git] / kernel / consteval.h

diff --git a/kernel/consteval.h b/kernel/consteval.h
index 09b4c434bb407814148f6e30d1c5a7730af47ba7..ff8cf86d62bb0f282fa37db6a918ef5aa30adec1 100644 (file)
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -91,10 +91,10 @@ struct ConstEval
        {
                if (cell->type == ID($lcu))
                {
-                       RTLIL::SigSpec sig_p = cell->getPort(ID(P));
-                       RTLIL::SigSpec sig_g = cell->getPort(ID(G));
-                       RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
-                       RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO))));
+                       RTLIL::SigSpec sig_p = cell->getPort(ID::P);
+                       RTLIL::SigSpec sig_g = cell->getPort(ID::G);
+                       RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+                       RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
 
                        if (sig_co.is_fully_const())
                                return true;
@@ -128,22 +128,22 @@ struct ConstEval
 
                RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-               log_assert(cell->hasPort(ID(Y)));
-               sig_y = values_map(assign_map(cell->getPort(ID(Y))));
+               log_assert(cell->hasPort(ID::Y));
+               sig_y = values_map(assign_map(cell->getPort(ID::Y)));
                if (sig_y.is_fully_const())
                        return true;
 
-               if (cell->hasPort(ID(S))) {
-                       sig_s = cell->getPort(ID(S));
+               if (cell->hasPort(ID::S)) {
+                       sig_s = cell->getPort(ID::S);
                        if (!eval(sig_s, undef, cell))
                                return false;
                }
 
-               if (cell->hasPort(ID(A)))
-                       sig_a = cell->getPort(ID(A));
+               if (cell->hasPort(ID::A))
+                       sig_a = cell->getPort(ID::A);
 
-               if (cell->hasPort(ID(B)))
-                       sig_b = cell->getPort(ID(B));
+               if (cell->hasPort(ID::B))
+                       sig_b = cell->getPort(ID::B);
 
                if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
                {
@@ -200,8 +200,8 @@ struct ConstEval
                }
                else if (cell->type == ID($fa))
                {
-                       RTLIL::SigSpec sig_c = cell->getPort(ID(C));
-                       RTLIL::SigSpec sig_x = cell->getPort(ID(X));
+                       RTLIL::SigSpec sig_c = cell->getPort(ID::C);
+                       RTLIL::SigSpec sig_x = cell->getPort(ID::X);
                        int width = GetSize(sig_c);
 
                        if (!eval(sig_a, undef, cell))
@@ -229,11 +229,11 @@ struct ConstEval
                }
                else if (cell->type == ID($alu))
                {
-                       bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool();
-                       bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool();
+                       bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
+                       bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
 
-                       RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
-                       RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
+                       RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
+                       RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
 
                        if (!eval(sig_a, undef, cell))
                                return false;
@@ -247,8 +247,8 @@ struct ConstEval
                        if (!eval(sig_bi, undef, cell))
                                return false;
 
-                       RTLIL::SigSpec sig_x = cell->getPort(ID(X));
-                       RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
+                       RTLIL::SigSpec sig_x = cell->getPort(ID::X);
+                       RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
 
                        bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
                        sig_a.extend_u0(GetSize(sig_y), signed_a);
@@ -298,21 +298,21 @@ struct ConstEval
                                        return false;
                        }
 
-                       RTLIL::Const result(0, GetSize(cell->getPort(ID(Y))));
+                       RTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));
                        if (!macc.eval(result))
                                log_abort();
 
-                       set(cell->getPort(ID(Y)), result);
+                       set(cell->getPort(ID::Y), result);
                }
                else
                {
                        RTLIL::SigSpec sig_c, sig_d;
 
                        if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
-                               if (cell->hasPort(ID(C)))
-                                       sig_c = cell->getPort(ID(C));
-                               if (cell->hasPort(ID(D)))
-                                       sig_d = cell->getPort(ID(D));
+                               if (cell->hasPort(ID::C))
+                                       sig_c = cell->getPort(ID::C);
+                               if (cell->hasPort(ID::D))
+                                       sig_d = cell->getPort(ID::D);
                        }
 
                        if (sig_a.size() > 0 && !eval(sig_a, undef, cell))