ice40: split out cells_map.v into ff_map.v
[yosys.git] / kernel / constids.inc
index 18be1222953c3884a4be9929d5458dab2a90c71d..6b40a590832e3389d378a1438a211d4f2407d10c 100644 (file)
 X(A)
-X(B)
-X(S)
-X(Y)
-X(keep)
-X(src)
-X(whitebox)
-X(blackbox)
+X(abc9_box)
+X(abc9_box_id)
+X(abc9_box_seq)
+X(abc9_carry)
+X(abc9_flop)
+X(abc9_holes)
+X(abc9_init)
+X(abc9_lut)
+X(abc9_mergeability)
+X(abc9_scc)
+X(abc9_scc_id)
+X(abcgroup)
+X(ABITS)
+X(ADDR)
 X(allconst)
 X(allseq)
+X(always_comb)
+X(always_ff)
+X(always_latch)
 X(anyconst)
 X(anyseq)
+X(ARST)
+X(ARST_POLARITY)
+X(ARST_VALUE)
+X(A_SIGNED)
+X(A_WIDTH)
+X(B)
+X(BI)
+X(blackbox)
+X(B_SIGNED)
+X(bugpoint_keep)
+X(B_WIDTH)
+X(C)
+X(cells_not_processed)
+X(CFG_ABITS)
+X(CFG_DBITS)
+X(CFG_INIT)
+X(CI)
+X(CLK)
+X(clkbuf_driver)
+X(clkbuf_inhibit)
+X(clkbuf_inv)
+X(clkbuf_sink)
+X(CLK_ENABLE)
+X(CLK_POLARITY)
+X(CLR)
+X(CLR_POLARITY)
+X(CO)
+X(CONFIG)
+X(CONFIG_WIDTH)
+X(CTRL_IN)
+X(CTRL_IN_WIDTH)
+X(CTRL_OUT)
+X(CTRL_OUT_WIDTH)
+X(D)
+X(DAT)
+X(DATA)
+X(DAT_DST_PEN)
+X(DAT_DST_POL)
 X(defaultvalue)
+X(DELAY)
+X(DEPTH)
+X(DST)
+X(DST_EN)
+X(DST_PEN)
+X(DST_POL)
+X(DST_WIDTH)
+X(dynports)
+X(E)
+X(EDGE_EN)
+X(EDGE_POL)
+X(EN)
+X(EN_DST)
+X(EN_POLARITY)
+X(EN_SRC)
+X(enum_base_type)
+X(enum_type)
+X(equiv_merged)
+X(equiv_region)
+X(extract_order)
+X(F)
 X(fsm_encoding)
+X(fsm_export)
+X(FULL)
 X(full_case)
+X(G)
 X(gclk)
+X(gentb_clock)
+X(gentb_constant)
+X(gentb_skip)
+X(H)
+X(hdlname)
+X(hierconn)
+X(I)
+X(INIT)
+X(init)
 X(initial_top)
+X(interface_modport)
+X(interfaces_replaced_in_module)
+X(interface_type)
+X(invertible_pin)
+X(iopad_external_pin)
 X(is_interface)
+X(J)
+X(K)
+X(keep)
+X(keep_hierarchy)
+X(L)
+X(lib_whitebox)
+X(localparam)
+X(LUT)
+X(lut_keep)
+X(M)
+X(maximize)
 X(mem2reg)
+X(MEMID)
+X(minimize)
+X(module_not_derived)
+X(N)
+X(NAME)
 X(noblackbox)
 X(nolatches)
+X(nomem2init)
 X(nomem2reg)
+X(nomeminit)
 X(nosync)
+X(nowrshmsk)
+X(O)
+X(OFFSET)
+X(onehot)
+X(P)
 X(parallel_case)
+X(parameter)
+X(PRIORITY)
+X(Q)
+X(qwp_position)
+X(R)
+X(RD_ADDR)
+X(RD_CLK)
+X(RD_CLK_ENABLE)
+X(RD_CLK_POLARITY)
+X(RD_DATA)
+X(RD_EN)
+X(RD_PORTS)
+X(RD_TRANSPARENT)
+X(reg)
+X(S)
+X(SET)
+X(SET_POLARITY)
+X(SIZE)
+X(SRC)
+X(src)
+X(SRC_DST_PEN)
+X(SRC_DST_POL)
+X(SRC_EN)
+X(SRC_PEN)
+X(SRC_POL)
+X(SRC_WIDTH)
+X(STATE_BITS)
+X(STATE_NUM)
+X(STATE_NUM_LOG2)
+X(STATE_RST)
+X(STATE_TABLE)
+X(submod)
+X(S_WIDTH)
+X(T)
+X(TABLE)
+X(techmap_autopurge)
+X(_TECHMAP_BITS_CONNMAP_)
+X(_TECHMAP_CELLTYPE_)
+X(techmap_celltype)
+X(techmap_maccmap)
+X(_TECHMAP_REPLACE_)
+X(techmap_simplemap)
+X(_techmap_special_)
+X(techmap_wrap)
+X(T_FALL_MAX)
+X(T_FALL_MIN)
+X(T_FALL_TYP)
+X(T_LIMIT)
+X(T_LIMIT2)
+X(T_LIMIT2_MAX)
+X(T_LIMIT2_MIN)
+X(T_LIMIT2_TYP)
+X(T_LIMIT_MAX)
+X(T_LIMIT_MIN)
+X(T_LIMIT_TYP)
+X(to_delete)
 X(top)
+X(TRANS_NUM)
+X(TRANSPARENT)
+X(TRANS_TABLE)
+X(T_RISE_MAX)
+X(T_RISE_MIN)
+X(T_RISE_TYP)
+X(TYPE)
+X(U)
+X(unique)
+X(unused_bits)
+X(V)
+X(via_celltype)
 X(wand)
+X(whitebox)
+X(WIDTH)
+X(wildcard_port_conns)
+X(wiretype)
 X(wor)
+X(WORDS)
+X(WR_ADDR)
+X(WR_CLK)
+X(WR_CLK_ENABLE)
+X(WR_CLK_POLARITY)
+X(WR_DATA)
+X(WR_EN)
+X(WR_PORTS)
+X(X)
+X(Y)
+X(Y_WIDTH)