/*
* yosys -- Yosys Open SYnthesis Suite
*
- * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
ports.clear();
bit_ports = cell->getPort(ID::B);
- std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
+ std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
int config_cursor = 0;
-#ifndef NDEBUG
- int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int();
+ int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
log_assert(GetSize(config_bits) >= config_width);
-#endif
int num_bits = 0;
if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
cell->setPort(ID::A, port_a);
cell->setPort(ID::B, bit_ports);
- cell->setParam(ID(CONFIG), config_bits);
- cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
- cell->setParam(ID(A_WIDTH), GetSize(port_a));
- cell->setParam(ID(B_WIDTH), GetSize(bit_ports));
+ cell->setParam(ID::CONFIG, config_bits);
+ cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
+ cell->setParam(ID::A_WIDTH, GetSize(port_a));
+ cell->setParam(ID::B_WIDTH, GetSize(bit_ports));
}
bool eval(RTLIL::Const &result) const