Change implicit conversions from bool to Sig* to explicit.

[yosys.git] / kernel / macc.h

diff --git a/kernel/macc.h b/kernel/macc.h
index c7595ebc18fe9f5aea803b965598ce0f002bb328..e4e1ebf52ab6a029e2c71445fc9fa9c62452e1b0 100644 (file)
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -99,18 +99,16 @@ struct Macc
 
        void from_cell(RTLIL::Cell *cell)
        {
-               RTLIL::SigSpec port_a = cell->getPort("\\A");
+               RTLIL::SigSpec port_a = cell->getPort(ID::A);
 
                ports.clear();
-               bit_ports = cell->getPort("\\B");
+               bit_ports = cell->getPort(ID::B);
 
-               std::vector<RTLIL::State> config_bits = cell->getParam("\\CONFIG").bits;
+               std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
                int config_cursor = 0;
 
-#ifndef NDEBUG
-               int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
+               int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
                log_assert(GetSize(config_bits) >= config_width);
-#endif
 
                int num_bits = 0;
                if (config_bits[config_cursor++] == State::S1) num_bits |= 1;
@@ -191,12 +189,12 @@ struct Macc
                        port_a.append(port.in_b);
                }
 
-               cell->setPort("\\A", port_a);
-               cell->setPort("\\B", bit_ports);
-               cell->setParam("\\CONFIG", config_bits);
-               cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits));
-               cell->setParam("\\A_WIDTH", GetSize(port_a));
-               cell->setParam("\\B_WIDTH", GetSize(bit_ports));
+               cell->setPort(ID::A, port_a);
+               cell->setPort(ID::B, bit_ports);
+               cell->setParam(ID::CONFIG, config_bits);
+               cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
+               cell->setParam(ID::A_WIDTH, GetSize(port_a));
+               cell->setParam(ID::B_WIDTH, GetSize(bit_ports));
        }
 
        bool eval(RTLIL::Const &result) const