Merge pull request #1853 from YosysHQ/eddie/fix_dynslice

[yosys.git] / kernel / macc.h

diff --git a/kernel/macc.h b/kernel/macc.h
index e07e7e01a8e9938b0c60fb76ba923a5c2c71d9f2..e9f6f05e914fdc36f41a7835fc1446d55ed4a2a2 100644 (file)
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -99,16 +99,16 @@ struct Macc
 
        void from_cell(RTLIL::Cell *cell)
        {
-               RTLIL::SigSpec port_a = cell->getPort(ID(A));
+               RTLIL::SigSpec port_a = cell->getPort(ID::A);
 
                ports.clear();
-               bit_ports = cell->getPort(ID(B));
+               bit_ports = cell->getPort(ID::B);
 
-               std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
+               std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
                int config_cursor = 0;
 
 #ifndef NDEBUG
-               int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int();
+               int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
                log_assert(GetSize(config_bits) >= config_width);
 #endif
 
@@ -191,12 +191,12 @@ struct Macc
                        port_a.append(port.in_b);
                }
 
-               cell->setPort(ID(A), port_a);
-               cell->setPort(ID(B), bit_ports);
-               cell->setParam(ID(CONFIG), config_bits);
-               cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
-               cell->setParam(ID(A_WIDTH), GetSize(port_a));
-               cell->setParam(ID(B_WIDTH), GetSize(bit_ports));
+               cell->setPort(ID::A, port_a);
+               cell->setPort(ID::B, bit_ports);
+               cell->setParam(ID::CONFIG, config_bits);
+               cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
+               cell->setParam(ID::A_WIDTH, GetSize(port_a));
+               cell->setParam(ID::B_WIDTH, GetSize(bit_ports));
        }
 
        bool eval(RTLIL::Const &result) const