Change implicit conversions from bool to Sig* to explicit.

[yosys.git] / kernel / modtools.h

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 29c510059ffc4f5e0220ffdeb6e9bea8eacffe0d..4cbaf78d0d6175cedff56a5a111538bc96bd281d 100644 (file)
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -1,7 +1,7 @@
 /* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -380,9 +380,11 @@ struct ModWalker
                }
        }
 
-       ModWalker(RTLIL::Design *design) : design(design), module(NULL)
+       ModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)
        {
-            ct.setup(design);
+               ct.setup(design);
+               if (module)
+                       setup(module);
        }
 
        void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
@@ -395,6 +397,8 @@ struct ModWalker
                signal_consumers.clear();
                signal_inputs.clear();
                signal_outputs.clear();
+               cell_inputs.clear();
+               cell_outputs.clear();
 
                for (auto &it : module->wires_)
                        add_wire(it.second);