Change implicit conversions from bool to Sig* to explicit.

[yosys.git] / kernel / modtools.h

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 69c13bd3b992e51ee70327d13acecfbc49a03d6c..4cbaf78d0d6175cedff56a5a111538bc96bd281d 100644 (file)
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -1,12 +1,12 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
- *  
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
  *  copyright notice and this permission notice appear in all copies.
- *  
+ *
  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor
 #endif
        }
 
-       virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
+       void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
        {
                log_assert(module == cell->module);
 
@@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
                port_add(cell, port, sig);
        }
 
-       virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
+       void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override
        {
                log_assert(module == mod);
 
@@ -180,8 +180,8 @@ struct ModIndex : public RTLIL::Monitor
                {
                        RTLIL::SigBit lhs = sigmap(sigsig.first[i]);
                        RTLIL::SigBit rhs = sigmap(sigsig.second[i]);
-                       bool has_lhs = database.count(lhs);
-                       bool has_rhs = database.count(rhs);
+                       bool has_lhs = database.count(lhs) != 0;
+                       bool has_rhs = database.count(rhs) != 0;
 
                        if (!has_lhs && !has_rhs) {
                                sigmap.add(lhs, rhs);
@@ -214,19 +214,19 @@ struct ModIndex : public RTLIL::Monitor
                }
        }
 
-       virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
+       void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override
        {
                log_assert(module == mod);
                auto_reload_module = true;
        }
 
-       virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
+       void notify_blackout(RTLIL::Module *mod) override
        {
                log_assert(module == mod);
                auto_reload_module = true;
        }
 
-       ModIndex(RTLIL::Module *_m) : module(_m)
+       ModIndex(RTLIL::Module *_m) : sigmap(_m), module(_m)
        {
                auto_reload_counter = 0;
                auto_reload_module = true;
@@ -274,6 +274,27 @@ struct ModIndex : public RTLIL::Monitor
                        return empty_result_set;
                return info->ports;
        }
+
+       void dump_db()
+       {
+               log("--- ModIndex Dump ---\n");
+
+               if (auto_reload_module) {
+                       log("AUTO-RELOAD\n");
+                       reload_module();
+               }
+
+               for (auto &it : database) {
+                       log("BIT %s:\n", log_signal(it.first));
+                       if (it.second.is_input)
+                               log("  PRIMARY INPUT\n");
+                       if (it.second.is_output)
+                               log("  PRIMARY OUTPUT\n");
+                       for (auto &port : it.second.ports)
+                               log("  PORT: %s.%s[%d] (%s)\n", log_id(port.cell),
+                                               log_id(port.port), port.offset, log_id(port.cell->type));
+               }
+       }
 };
 
 struct ModWalker
@@ -359,28 +380,25 @@ struct ModWalker
                }
        }
 
-       ModWalker() : design(NULL), module(NULL)
-       {
-       }
-
-       ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
+       ModWalker(RTLIL::Design *design, RTLIL::Module *module = nullptr) : design(design), module(NULL)
        {
-               setup(design, module, filter_ct);
+               ct.setup(design);
+               if (module)
+                       setup(module);
        }
 
-       void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL)
+       void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL)
        {
-               this->design = design;
                this->module = module;
 
-               ct.clear();
-               ct.setup(design);
                sigmap.set(module);
 
                signal_drivers.clear();
                signal_consumers.clear();
                signal_inputs.clear();
                signal_outputs.clear();
+               cell_inputs.clear();
+               cell_outputs.clear();
 
                for (auto &it : module->wires_)
                        add_wire(it.second);