*/
#include "kernel/yosys.h"
+#include "kernel/macc.h"
#include "frontends/verilog/verilog_frontend.h"
#include "backends/ilang/ilang_backend.h"
YOSYS_NAMESPACE_BEGIN
+RTLIL::IdString::destruct_guard_t RTLIL::IdString::destruct_guard;
std::vector<int> RTLIL::IdString::global_refcount_storage_;
std::vector<char*> RTLIL::IdString::global_id_storage_;
std::map<char*, int, RTLIL::IdString::char_ptr_cmp> RTLIL::IdString::global_id_index_;
bits.push_back(bit);
}
+RTLIL::Const::Const(const std::vector<bool> &bits)
+{
+ flags = RTLIL::CONST_FLAG_NONE;
+ for (auto b : bits)
+ this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
+}
+
bool RTLIL::Const::operator <(const RTLIL::Const &other) const
{
if (bits.size() != other.bits.size())
return false;
}
-int RTLIL::Const::as_int() const
+int RTLIL::Const::as_int(bool is_signed) const
{
- int ret = 0;
+ int32_t ret = 0;
for (size_t i = 0; i < bits.size() && i < 32; i++)
if (bits[i] == RTLIL::S1)
ret |= 1 << i;
+ if (is_signed && bits.back() == RTLIL::S1)
+ for (size_t i = bits.size(); i < 32; i++)
+ ret |= 1 << i;
return ret;
}
RTLIL::Design::Design()
{
refcount_modules_ = 0;
+ selection_stack.push_back(RTLIL::Selection());
}
RTLIL::Design::~Design()
return module;
}
+void RTLIL::Design::scratchpad_unset(std::string varname)
+{
+ scratchpad.erase(varname);
+}
+
+void RTLIL::Design::scratchpad_set_int(std::string varname, int value)
+{
+ scratchpad[varname] = stringf("%d", value);
+}
+
+void RTLIL::Design::scratchpad_set_bool(std::string varname, bool value)
+{
+ scratchpad[varname] = value ? "true" : "false";
+}
+
+void RTLIL::Design::scratchpad_set_string(std::string varname, std::string value)
+{
+ scratchpad[varname] = value;
+}
+
+int RTLIL::Design::scratchpad_get_int(std::string varname, int default_value) const
+{
+ if (scratchpad.count(varname) == 0)
+ return default_value;
+
+ std::string str = scratchpad.at(varname);
+
+ if (str == "0" || str == "false")
+ return 0;
+
+ if (str == "1" || str == "true")
+ return 1;
+
+ char *endptr = nullptr;
+ long int parsed_value = strtol(str.c_str(), &endptr, 10);
+ return *endptr ? default_value : parsed_value;
+}
+
+bool RTLIL::Design::scratchpad_get_bool(std::string varname, bool default_value) const
+{
+ if (scratchpad.count(varname) == 0)
+ return default_value;
+
+ std::string str = scratchpad.at(varname);
+
+ if (str == "0" || str == "false")
+ return false;
+
+ if (str == "1" || str == "true")
+ return true;
+
+ return default_value;
+}
+
+std::string RTLIL::Design::scratchpad_get_string(std::string varname, std::string default_value) const
+{
+ if (scratchpad.count(varname) == 0)
+ return default_value;
+ return scratchpad.at(varname);
+}
+
void RTLIL::Design::remove(RTLIL::Module *module)
{
for (auto mon : monitors)
if (selected_whole_module(it.first))
result.push_back(it.second);
else if (selected_module(it.first))
- log("Warning: Ignoring partially selected module %s.\n", log_id(it.first));
+ log_warning("Ignoring partially selected module %s.\n", log_id(it.first));
return result;
}
void error(int linenr)
{
- char *ptr;
- size_t size;
-
- FILE *f = open_memstream(&ptr, &size);
- ILANG_BACKEND::dump_cell(f, " ", cell);
- fputc(0, f);
- fclose(f);
+ std::stringstream buf;
+ ILANG_BACKEND::dump_cell(buf, " ", cell);
log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
module ? module->name.c_str() : "", module ? "." : "",
- cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, ptr);
+ cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
}
int param(const char *name)
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
return;
- if (cell->type.in("$not", "$pos", "$bu0", "$neg")) {
+ if (cell->type.in("$not", "$pos", "$neg")) {
param_bool("\\A_SIGNED");
port("\\A", param("\\A_WIDTH"));
port("\\Y", param("\\Y_WIDTH"));
return;
}
+ if (cell->type == "$fa") {
+ port("\\A", param("\\WIDTH"));
+ port("\\B", param("\\WIDTH"));
+ port("\\C", param("\\WIDTH"));
+ port("\\X", param("\\WIDTH"));
+ port("\\Y", param("\\WIDTH"));
+ check_expected();
+ return;
+ }
+
+ if (cell->type == "$lcu") {
+ port("\\P", param("\\WIDTH"));
+ port("\\G", param("\\WIDTH"));
+ port("\\CI", 1);
+ port("\\CO", param("\\WIDTH"));
+ check_expected();
+ return;
+ }
+
+ if (cell->type == "$alu") {
+ param_bool("\\A_SIGNED");
+ param_bool("\\B_SIGNED");
+ port("\\A", param("\\A_WIDTH"));
+ port("\\B", param("\\B_WIDTH"));
+ port("\\CI", 1);
+ port("\\BI", 1);
+ port("\\X", param("\\Y_WIDTH"));
+ port("\\Y", param("\\Y_WIDTH"));
+ port("\\CO", param("\\Y_WIDTH"));
+ check_expected();
+ return;
+ }
+
+ if (cell->type == "$macc") {
+ param("\\CONFIG");
+ param("\\CONFIG_WIDTH");
+ port("\\A", param("\\A_WIDTH"));
+ port("\\B", param("\\B_WIDTH"));
+ port("\\Y", param("\\Y_WIDTH"));
+ check_expected();
+ Macc().from_cell(cell);
+ return;
+ }
+
if (cell->type == "$logic_not") {
param_bool("\\A_SIGNED");
port("\\A", param("\\A_WIDTH"));
if (cell->type == "$lut") {
param("\\LUT");
- port("\\I", param("\\WIDTH"));
- port("\\O", 1);
+ port("\\A", param("\\WIDTH"));
+ port("\\Y", 1);
check_expected();
return;
}
return;
}
+ if (cell->type == "$dffe") {
+ param_bool("\\CLK_POLARITY");
+ param_bool("\\EN_POLARITY");
+ port("\\CLK", 1);
+ port("\\EN", 1);
+ port("\\D", param("\\WIDTH"));
+ port("\\Q", param("\\WIDTH"));
+ check_expected();
+ return;
+ }
+
if (cell->type == "$dffsr") {
param_bool("\\CLK_POLARITY");
param_bool("\\SET_POLARITY");
return;
}
- if (cell->type == "$_INV_") { check_gate("AY"); return; }
- if (cell->type == "$_AND_") { check_gate("ABY"); return; }
- if (cell->type == "$_OR_") { check_gate("ABY"); return; }
- if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
- if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
+ if (cell->type == "$_BUF_") { check_gate("AY"); return; }
+ if (cell->type == "$_NOT_") { check_gate("AY"); return; }
+ if (cell->type == "$_AND_") { check_gate("ABY"); return; }
+ if (cell->type == "$_NAND_") { check_gate("ABY"); return; }
+ if (cell->type == "$_OR_") { check_gate("ABY"); return; }
+ if (cell->type == "$_NOR_") { check_gate("ABY"); return; }
+ if (cell->type == "$_XOR_") { check_gate("ABY"); return; }
+ if (cell->type == "$_XNOR_") { check_gate("ABY"); return; }
+ if (cell->type == "$_MUX_") { check_gate("ABSY"); return; }
+ if (cell->type == "$_AOI3_") { check_gate("ABCY"); return; }
+ if (cell->type == "$_OAI3_") { check_gate("ABCY"); return; }
+ if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
+ if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
if (cell->type == "$_SR_NN_") { check_gate("SRQ"); return; }
if (cell->type == "$_SR_NP_") { check_gate("SRQ"); return; }
if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; }
if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; }
+ if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; }
+ if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; }
+ if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; }
+ if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; }
+
if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; }
if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; }
if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; }
for (auto &it2 : it.second->attributes)
log_assert(!it2.first.empty());
if (it.second->port_id) {
- log_assert(SIZE(ports) >= it.second->port_id);
+ log_assert(GetSize(ports) >= it.second->port_id);
log_assert(ports.at(it.second->port_id-1) == it.first);
log_assert(it.second->port_input || it.second->port_output);
- if (SIZE(ports_declared) < it.second->port_id)
+ if (GetSize(ports_declared) < it.second->port_id)
ports_declared.resize(it.second->port_id);
log_assert(ports_declared[it.second->port_id-1] == false);
ports_declared[it.second->port_id-1] = true;
}
for (auto port_declared : ports_declared)
log_assert(port_declared == true);
- log_assert(SIZE(ports) == SIZE(ports_declared));
+ log_assert(GetSize(ports) == GetSize(ports_declared));
for (auto &it : memories) {
log_assert(it.first == it.second->name);
bool RTLIL::Module::has_memories_warn() const
{
if (!memories.empty())
- log("Warning: Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
+ log_warning("Ignoring module %s because it contains memories (run 'memory' command first).\n", log_id(this));
return !memories.empty();
}
bool RTLIL::Module::has_processes_warn() const
{
if (!processes.empty())
- log("Warning: Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
+ log_warning("Ignoring module %s because it contains processes (run 'proc' command first).\n", log_id(this));
return !processes.empty();
}
void RTLIL::Module::remove(RTLIL::Cell *cell)
{
+ while (!cell->connections_.empty())
+ cell->unsetPort(cell->connections_.begin()->first);
+
log_assert(cells_.count(cell->name) != 0);
log_assert(refcount_cells_ == 0);
cells_.erase(cell->name);
cells_[c2->name] = c2;
}
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
+{
+ int index = 0;
+ return uniquify(name, index);
+}
+
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
+{
+ if (index == 0) {
+ if (count_id(name) == 0)
+ return name;
+ index++;
+ }
+
+ while (1) {
+ RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
+ if (count_id(new_name) == 0)
+ return new_name;
+ index++;
+ }
+}
+
static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
{
if (a->port_id && !b->port_id)
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, bool is_signed) { \
RTLIL::Cell *cell = addCell(name, _type); \
cell->parameters["\\A_SIGNED"] = is_signed; \
- cell->parameters["\\A_WIDTH"] = sig_a.size(); \
- cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
- cell->setPort("\\A", sig_a); \
- cell->setPort("\\Y", sig_y); \
+ cell->parameters["\\A_WIDTH"] = sig_a.size(); \
+ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
+ cell->setPort("\\A", sig_a); \
+ cell->setPort("\\Y", sig_y); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed) { \
}
DEF_METHOD(Not, sig_a.size(), "$not")
DEF_METHOD(Pos, sig_a.size(), "$pos")
-DEF_METHOD(Bu0, sig_a.size(), "$bu0")
DEF_METHOD(Neg, sig_a.size(), "$neg")
DEF_METHOD(ReduceAnd, 1, "$reduce_and")
DEF_METHOD(ReduceOr, 1, "$reduce_or")
RTLIL::Cell *cell = addCell(name, _type); \
cell->parameters["\\A_SIGNED"] = is_signed; \
cell->parameters["\\B_SIGNED"] = is_signed; \
- cell->parameters["\\A_WIDTH"] = sig_a.size(); \
- cell->parameters["\\B_WIDTH"] = sig_b.size(); \
- cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
- cell->setPort("\\A", sig_a); \
- cell->setPort("\\B", sig_b); \
- cell->setPort("\\Y", sig_y); \
+ cell->parameters["\\A_WIDTH"] = sig_a.size(); \
+ cell->parameters["\\B_WIDTH"] = sig_b.size(); \
+ cell->parameters["\\Y_WIDTH"] = sig_y.size(); \
+ cell->setPort("\\A", sig_a); \
+ cell->setPort("\\B", sig_b); \
+ cell->setPort("\\Y", sig_y); \
return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, bool is_signed) { \
#define DEF_METHOD(_func, _type, _pmux) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y) { \
- RTLIL::Cell *cell = addCell(name, _type); \
+ RTLIL::Cell *cell = addCell(name, _type); \
cell->parameters["\\WIDTH"] = sig_a.size(); \
- cell->parameters["\\WIDTH"] = sig_b.size(); \
if (_pmux) cell->parameters["\\S_WIDTH"] = sig_s.size(); \
- cell->setPort("\\A", sig_a); \
- cell->setPort("\\B", sig_b); \
- cell->setPort("\\S", sig_s); \
- cell->setPort("\\Y", sig_y); \
- return cell; \
+ cell->setPort("\\A", sig_a); \
+ cell->setPort("\\B", sig_b); \
+ cell->setPort("\\S", sig_s); \
+ cell->setPort("\\Y", sig_y); \
+ return cell; \
} \
RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s) { \
RTLIL::SigSpec sig_y = addWire(NEW_ID, sig_a.size()); \
- add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
- return sig_y; \
+ add ## _func(name, sig_a, sig_b, sig_s, sig_y); \
+ return sig_y; \
}
DEF_METHOD(Mux, "$mux", 0)
DEF_METHOD(Pmux, "$pmux", 1)
#undef DEF_METHOD
#define DEF_METHOD_2(_func, _type, _P1, _P2) \
- RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
- RTLIL::Cell *cell = addCell(name, _type); \
- cell->setPort("\\" #_P1, sig1); \
- cell->setPort("\\" #_P2, sig2); \
- return cell; \
+ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
+ RTLIL::Cell *cell = addCell(name, _type); \
+ cell->setPort("\\" #_P1, sig1); \
+ cell->setPort("\\" #_P2, sig2); \
+ return cell; \
} \
- RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1) { \
- RTLIL::SigSpec sig2 = addWire(NEW_ID); \
- add ## _func(name, sig1, sig2); \
- return sig2; \
+ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1) { \
+ RTLIL::SigBit sig2 = addWire(NEW_ID); \
+ add ## _func(name, sig1, sig2); \
+ return sig2; \
}
#define DEF_METHOD_3(_func, _type, _P1, _P2, _P3) \
- RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
- RTLIL::Cell *cell = addCell(name, _type); \
- cell->setPort("\\" #_P1, sig1); \
- cell->setPort("\\" #_P2, sig2); \
- cell->setPort("\\" #_P3, sig3); \
- return cell; \
+ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
+ RTLIL::Cell *cell = addCell(name, _type); \
+ cell->setPort("\\" #_P1, sig1); \
+ cell->setPort("\\" #_P2, sig2); \
+ cell->setPort("\\" #_P3, sig3); \
+ return cell; \
} \
- RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2) { \
- RTLIL::SigSpec sig3 = addWire(NEW_ID); \
- add ## _func(name, sig1, sig2, sig3); \
- return sig3; \
+ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2) { \
+ RTLIL::SigBit sig3 = addWire(NEW_ID); \
+ add ## _func(name, sig1, sig2, sig3); \
+ return sig3; \
}
#define DEF_METHOD_4(_func, _type, _P1, _P2, _P3, _P4) \
- RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3, RTLIL::SigSpec sig4) { \
- RTLIL::Cell *cell = addCell(name, _type); \
- cell->setPort("\\" #_P1, sig1); \
- cell->setPort("\\" #_P2, sig2); \
- cell->setPort("\\" #_P3, sig3); \
- cell->setPort("\\" #_P4, sig4); \
- return cell; \
+ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
+ RTLIL::Cell *cell = addCell(name, _type); \
+ cell->setPort("\\" #_P1, sig1); \
+ cell->setPort("\\" #_P2, sig2); \
+ cell->setPort("\\" #_P3, sig3); \
+ cell->setPort("\\" #_P4, sig4); \
+ return cell; \
} \
- RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig1, RTLIL::SigSpec sig2, RTLIL::SigSpec sig3) { \
- RTLIL::SigSpec sig4 = addWire(NEW_ID); \
- add ## _func(name, sig1, sig2, sig3, sig4); \
- return sig4; \
+ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3) { \
+ RTLIL::SigBit sig4 = addWire(NEW_ID); \
+ add ## _func(name, sig1, sig2, sig3, sig4); \
+ return sig4; \
}
-DEF_METHOD_2(InvGate, "$_INV_", A, Y)
-DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
-DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
-DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
-DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
+#define DEF_METHOD_5(_func, _type, _P1, _P2, _P3, _P4, _P5) \
+ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4, RTLIL::SigBit sig5) { \
+ RTLIL::Cell *cell = addCell(name, _type); \
+ cell->setPort("\\" #_P1, sig1); \
+ cell->setPort("\\" #_P2, sig2); \
+ cell->setPort("\\" #_P3, sig3); \
+ cell->setPort("\\" #_P4, sig4); \
+ cell->setPort("\\" #_P5, sig5); \
+ return cell; \
+ } \
+ RTLIL::SigBit RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigBit sig1, RTLIL::SigBit sig2, RTLIL::SigBit sig3, RTLIL::SigBit sig4) { \
+ RTLIL::SigBit sig5 = addWire(NEW_ID); \
+ add ## _func(name, sig1, sig2, sig3, sig4, sig5); \
+ return sig5; \
+ }
+DEF_METHOD_2(NotGate, "$_NOT_", A, Y)
+DEF_METHOD_3(AndGate, "$_AND_", A, B, Y)
+DEF_METHOD_3(NandGate, "$_NAND_", A, B, Y)
+DEF_METHOD_3(OrGate, "$_OR_", A, B, Y)
+DEF_METHOD_3(NorGate, "$_NOR_", A, B, Y)
+DEF_METHOD_3(XorGate, "$_XOR_", A, B, Y)
+DEF_METHOD_3(XnorGate, "$_XNOR_", A, B, Y)
+DEF_METHOD_4(MuxGate, "$_MUX_", A, B, S, Y)
+DEF_METHOD_4(Aoi3Gate, "$_AOI3_", A, B, C, Y)
+DEF_METHOD_4(Oai3Gate, "$_OAI3_", A, B, C, Y)
+DEF_METHOD_5(Aoi4Gate, "$_AOI4_", A, B, C, D, Y)
+DEF_METHOD_5(Oai4Gate, "$_OAI4_", A, B, C, D, Y)
#undef DEF_METHOD_2
#undef DEF_METHOD_3
#undef DEF_METHOD_4
+#undef DEF_METHOD_5
RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool a_signed, bool b_signed)
{
RTLIL::Cell *cell = addCell(name, "$lut");
cell->parameters["\\LUT"] = lut;
cell->parameters["\\WIDTH"] = sig_i.size();
- cell->setPort("\\I", sig_i);
- cell->setPort("\\O", sig_o);
+ cell->setPort("\\A", sig_i);
+ cell->setPort("\\Y", sig_o);
return cell;
}
return cell;
}
-RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
+RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity)
{
RTLIL::Cell *cell = addCell(name, "$dff");
cell->parameters["\\CLK_POLARITY"] = clk_polarity;
return cell;
}
+RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
+{
+ RTLIL::Cell *cell = addCell(name, "$dffe");
+ cell->parameters["\\CLK_POLARITY"] = clk_polarity;
+ cell->parameters["\\EN_POLARITY"] = en_polarity;
+ cell->parameters["\\WIDTH"] = sig_q.size();
+ cell->setPort("\\CLK", sig_clk);
+ cell->setPort("\\EN", sig_en);
+ cell->setPort("\\D", sig_d);
+ cell->setPort("\\Q", sig_q);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDffsr(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
{
return cell;
}
+RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool en_polarity)
+{
+ RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
+ cell->setPort("\\C", sig_clk);
+ cell->setPort("\\E", sig_en);
+ cell->setPort("\\D", sig_d);
+ cell->setPort("\\Q", sig_q);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addDffsrGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_set, RTLIL::SigSpec sig_clr,
RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity)
{
size = 0;
}
+RTLIL::Cell::Cell() : module(nullptr)
+{
+}
+
bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
{
return connections_.count(portname) != 0;
bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
{
- return parameters.count(paramname);
+ return parameters.count(paramname) != 0;
}
void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
return;
- if (type == "$mux" || type == "$pmux")
- {
- parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+ if (type == "$mux" || type == "$pmux") {
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
if (type == "$pmux")
- parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
+ parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
check();
return;
}
- bool signedness_ab = type != "$slice" && type != "$concat";
+ if (type == "$lut") {
+ parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
+ return;
+ }
+
+ if (type == "$fa") {
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
+ return;
+ }
+
+ if (type == "$lcu") {
+ parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
+ return;
+ }
+
+ bool signedness_ab = !type.in("$slice", "$concat", "$macc");
if (connections_.count("\\A")) {
if (signedness_ab) {
else if (parameters.count("\\A_SIGNED") == 0)
parameters["\\A_SIGNED"] = false;
}
- parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
+ parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
}
if (connections_.count("\\B")) {
else if (parameters.count("\\B_SIGNED") == 0)
parameters["\\B_SIGNED"] = false;
}
- parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
+ parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
}
if (connections_.count("\\Y"))
- parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
check();
}
RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
{
wire = NULL;
- data = value;
- width = data.bits.size();
+ data = value.bits;
+ width = GetSize(data);
offset = 0;
}
RTLIL::SigChunk::SigChunk(const std::string &str)
{
wire = NULL;
- data = RTLIL::Const(str);
- width = data.bits.size();
+ data = RTLIL::Const(str).bits;
+ width = GetSize(data);
offset = 0;
}
RTLIL::SigChunk::SigChunk(int val, int width)
{
wire = NULL;
- data = RTLIL::Const(val, width);
- this->width = data.bits.size();
+ data = RTLIL::Const(val, width).bits;
+ this->width = GetSize(data);
offset = 0;
}
RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
{
wire = NULL;
- data = RTLIL::Const(bit, width);
- this->width = data.bits.size();
+ data = RTLIL::Const(bit, width).bits;
+ this->width = GetSize(data);
offset = 0;
}
wire = bit.wire;
offset = 0;
if (wire == NULL)
- data = RTLIL::Const(bit.data);
+ data = RTLIL::Const(bit.data).bits;
else
offset = bit.offset;
width = 1;
ret.width = length;
} else {
for (int i = 0; i < length; i++)
- ret.data.bits.push_back(data.bits[offset+i]);
+ ret.data.push_back(data[offset+i]);
ret.width = length;
}
return ret;
if (width != other.width)
return width < other.width;
- return data.bits < other.data.bits;
+ return data < other.data;
}
bool RTLIL::SigChunk::operator ==(const RTLIL::SigChunk &other) const
{
- if (wire != other.wire || width != other.width || offset != other.offset)
- return false;
- if (data.bits != other.data.bits)
- return false;
- return true;
+ return wire == other.wire && width == other.width && offset == other.offset && data == other.data;
}
bool RTLIL::SigChunk::operator !=(const RTLIL::SigChunk &other) const
for (auto &bit : other.bits_) {
if (last && bit.wire == last->wire) {
if (bit.wire == NULL) {
- last->data.bits.push_back(bit.data);
+ last->data.push_back(bit.data);
last->width++;
continue;
} else if (last_end_offset == bit.offset) {
check();
}
+RTLIL::SigSpec::SigSpec(bool bit)
+{
+ cover("kernel.rtlil.sigspec.init.bool");
+
+ width_ = 0;
+ hash_ = 0;
+ append_bit(bit);
+ check();
+}
+
void RTLIL::SigSpec::pack() const
{
RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;
for (auto &bit : old_bits) {
if (last && bit.wire == last->wire) {
if (bit.wire == NULL) {
- last->data.bits.push_back(bit.data);
+ last->data.push_back(bit.data);
last->width++;
continue;
} else if (last_end_offset == bit.offset) {
that->hash_ = 0;
}
-#define DJB2(_hash, _value) do { (_hash) = (((_hash) << 5) + (_hash)) + (_value); } while (0)
+#define DJB2(_hash, _value) (_hash) = (((_hash) << 5) + (_hash)) + (_value)
void RTLIL::SigSpec::hash() const
{
that->hash_ = 5381;
for (auto &c : that->chunks_)
if (c.wire == NULL) {
- for (auto &v : c.data.bits)
+ for (auto &v : c.data)
DJB2(that->hash_, v);
} else {
DJB2(that->hash_, c.wire->name.index_);
std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
- for (int i = 0; i < SIZE(pattern.bits_); i++)
+ for (int i = 0; i < GetSize(pattern.bits_); i++)
if (pattern.bits_[i].wire != NULL)
rules[pattern.bits_[i]] = with.bits_[i];
unpack();
other->unpack();
- for (int i = 0; i < SIZE(bits_); i++) {
+ for (int i = 0; i < GetSize(bits_); i++) {
auto it = rules.find(bits_[i]);
if (it != rules.end())
other->bits_[i] = it->second;
std::vector<RTLIL::SigBit> new_bits, new_other_bits;
- for (int i = 0; i < SIZE(bits_); i++) {
+ new_bits.resize(GetSize(bits_));
+ if (other != NULL)
+ new_other_bits.resize(GetSize(bits_));
+
+ int k = 0;
+ for (int i = 0; i < GetSize(bits_); i++) {
if (bits_[i].wire != NULL && pattern.count(bits_[i]))
continue;
if (other != NULL)
- new_other_bits.push_back(other->bits_[i]);
- new_bits.push_back(bits_[i]);
+ new_other_bits[k] = other->bits_[i];
+ new_bits[k++] = bits_[i];
}
+ new_bits.resize(k);
+ if (other != NULL)
+ new_other_bits.resize(k);
+
bits_.swap(new_bits);
- width_ = SIZE(bits_);
+ width_ = GetSize(bits_);
if (other != NULL) {
other->bits_.swap(new_other_bits);
- other->width_ = SIZE(other->bits_);
+ other->width_ = GetSize(other->bits_);
}
check();
cover("kernel.rtlil.sigspec.remove_const.packed");
std::vector<RTLIL::SigChunk> new_chunks;
- new_chunks.reserve(SIZE(chunks_));
+ new_chunks.reserve(GetSize(chunks_));
width_ = 0;
for (auto &chunk : chunks_)
{
auto &my_last_c = chunks_.back();
if (my_last_c.wire == NULL && other_c.wire == NULL) {
- auto &this_data = my_last_c.data.bits;
- auto &other_data = other_c.data.bits;
+ auto &this_data = my_last_c.data;
+ auto &other_data = other_c.data;
this_data.insert(this_data.end(), other_data.begin(), other_data.end());
my_last_c.width += other_c.width;
} else
else
if (bit.wire == NULL)
if (chunks_.back().wire == NULL) {
- chunks_.back().data.bits.push_back(bit.data);
+ chunks_.back().data.push_back(bit.data);
chunks_.back().width++;
} else
chunks_.push_back(bit);
check();
}
-void RTLIL::SigSpec::extend(int width, bool is_signed)
+void RTLIL::SigSpec::extend_xx(int width, bool is_signed)
{
- cover("kernel.rtlil.sigspec.extend");
+ cover("kernel.rtlil.sigspec.extend_xx");
pack();
remove(width, width_ - width);
if (width_ < width) {
- RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
- if (!is_signed && padding != RTLIL::SigSpec(RTLIL::State::Sx) && padding != RTLIL::SigSpec(RTLIL::State::Sz) &&
- padding != RTLIL::SigSpec(RTLIL::State::Sa) && padding != RTLIL::SigSpec(RTLIL::State::Sm))
- padding = RTLIL::SigSpec(RTLIL::State::S0);
+ RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
+ if (!is_signed && (padding == RTLIL::State::S1 || padding.wire))
+ padding = RTLIL::State::S0;
while (width_ < width)
append(padding);
}
remove(width, width_ - width);
if (width_ < width) {
- RTLIL::SigSpec padding = width_ > 0 ? extract(width_ - 1, 1) : RTLIL::SigSpec(RTLIL::State::S0);
+ RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
if (!is_signed)
- padding = RTLIL::SigSpec(RTLIL::State::S0);
+ padding = RTLIL::State::S0;
while (width_ < width)
append(padding);
}
if (i > 0)
log_assert(chunks_[i-1].wire != NULL);
log_assert(chunk.offset == 0);
- log_assert(chunk.data.bits.size() == (size_t)chunk.width);
+ log_assert(chunk.data.size() == (size_t)chunk.width);
} else {
if (i > 0 && chunks_[i-1].wire == chunk.wire)
log_assert(chunk.offset != chunks_[i-1].offset + chunks_[i-1].width);
log_assert(chunk.offset >= 0);
log_assert(chunk.width >= 0);
log_assert(chunk.offset + chunk.width <= chunk.wire->width);
- log_assert(chunk.data.bits.size() == 0);
+ log_assert(chunk.data.size() == 0);
}
w += chunk.width;
}
{
cover("kernel.rtlil.sigspec.check.unpacked");
- log_assert(width_ == SIZE(bits_));
+ log_assert(width_ == GetSize(bits_));
log_assert(chunks_.empty());
}
}
cover("kernel.rtlil.sigspec.is_wire");
pack();
- return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
+ return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
}
bool RTLIL::SigSpec::is_chunk() const
cover("kernel.rtlil.sigspec.is_chunk");
pack();
- return SIZE(chunks_) == 1;
+ return GetSize(chunks_) == 1;
}
bool RTLIL::SigSpec::is_fully_const() const
for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
if (it->width > 0 && it->wire != NULL)
return false;
- for (size_t i = 0; i < it->data.bits.size(); i++)
- if (it->data.bits[i] != RTLIL::State::S0 && it->data.bits[i] != RTLIL::State::S1)
+ for (size_t i = 0; i < it->data.size(); i++)
+ if (it->data[i] != RTLIL::State::S0 && it->data[i] != RTLIL::State::S1)
return false;
}
return true;
for (auto it = chunks_.begin(); it != chunks_.end(); it++) {
if (it->width > 0 && it->wire != NULL)
return false;
- for (size_t i = 0; i < it->data.bits.size(); i++)
- if (it->data.bits[i] != RTLIL::State::Sx && it->data.bits[i] != RTLIL::State::Sz)
+ for (size_t i = 0; i < it->data.size(); i++)
+ if (it->data[i] != RTLIL::State::Sx && it->data[i] != RTLIL::State::Sz)
return false;
}
return true;
pack();
for (auto it = chunks_.begin(); it != chunks_.end(); it++)
if (it->width > 0 && it->wire == NULL) {
- for (size_t i = 0; i < it->data.bits.size(); i++)
- if (it->data.bits[i] == RTLIL::State::Sm)
+ for (size_t i = 0; i < it->data.size(); i++)
+ if (it->data[i] == RTLIL::State::Sm)
return true;
}
return false;
cover("kernel.rtlil.sigspec.as_bool");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
- return chunks_[0].data.as_bool();
+ return RTLIL::Const(chunks_[0].data).as_bool();
return false;
}
-int RTLIL::SigSpec::as_int() const
+int RTLIL::SigSpec::as_int(bool is_signed) const
{
cover("kernel.rtlil.sigspec.as_int");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
- return chunks_[0].data.as_int();
+ return RTLIL::Const(chunks_[0].data).as_int(is_signed);
return 0;
}
for (int j = 0; j < chunk.width; j++)
str += "?";
else
- str += chunk.data.as_string();
+ str += RTLIL::Const(chunk.data).as_string();
}
return str;
}
cover("kernel.rtlil.sigspec.as_const");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return chunks_[0].data;
return RTLIL::Const();
if (netname.size() == 0)
continue;
- if ('0' <= netname[0] && netname[0] <= '9') {
+ if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
cover("kernel.rtlil.sigspec.parse.const");
AST::get_line_num = sigspec_parse_get_dummy_line_num;
AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname);
sigspec_parse_split(index_tokens, indices.substr(1, indices.size()-2), ':');
if (index_tokens.size() == 1) {
cover("kernel.rtlil.sigspec.parse.bit_sel");
- sig.append(RTLIL::SigSpec(wire, atoi(index_tokens.at(0).c_str())));
+ int a = atoi(index_tokens.at(0).c_str());
+ if (a < 0 || a >= wire->width)
+ return false;
+ sig.append(RTLIL::SigSpec(wire, a));
} else {
cover("kernel.rtlil.sigspec.parse.part_sel");
int a = atoi(index_tokens.at(0).c_str());
int tmp = a;
a = b, b = tmp;
}
+ if (a < 0 || a >= wire->width)
+ return false;
+ if (b < 0 || b >= wire->width)
+ return false;
sig.append(RTLIL::SigSpec(wire, a, b-a+1));
}
} else
if (lhs.chunks_.size() == 1) {
char *p = (char*)str.c_str(), *endptr;
- long long int val = strtoll(p, &endptr, 10);
+ long int val = strtol(p, &endptr, 10);
if (endptr && endptr != p && *endptr == 0) {
sig = RTLIL::SigSpec(val, lhs.width_);
cover("kernel.rtlil.sigspec.parse.rhs_dec");
projects / yosys.git / blobdiff