return true;
}
+bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
+{
+ return attributes.count(id);
+}
+
void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
{
if (value)
return it->second.as_bool();
}
+void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
+{
+ if (value.empty())
+ attributes.erase(id);
+ else
+ attributes[id] = value;
+}
+
+string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
+{
+ std::string value;
+ const auto it = attributes.find(id);
+ if (it != attributes.end())
+ value = it->second.decode_string();
+ return value;
+}
+
void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
{
string attrval;
return data;
}
-void RTLIL::AttrObject::set_src_attribute(const std::string &src)
-{
- if (src.empty())
- attributes.erase(ID::src);
- else
- attributes[ID::src] = src;
-}
-
-std::string RTLIL::AttrObject::get_src_attribute() const
-{
- std::string src;
- const auto it = attributes.find(ID::src);
- if (it != attributes.end())
- src = it->second.decode_string();
- return src;
-}
-
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
}
log_assert(modules_.at(module->name) == module);
+ log_assert(refcount_modules_ == 0);
modules_.erase(module->name);
delete module;
}
delete it->second;
processes.clear();
+ connections_.clear();
+
remove(delwires);
set_bool_attribute(ID::blackbox);
}
{
wires_.sort(sort_by_id_str());
cells_.sort(sort_by_id_str());
- avail_parameters.sort(sort_by_id_str());
+ parameter_default_values.sort(sort_by_id_str());
memories.sort(sort_by_id_str());
processes.sort(sort_by_id_str());
for (auto &it : cells_)
log_assert(new_mod->refcount_cells_ == 0);
new_mod->avail_parameters = avail_parameters;
+ new_mod->parameter_default_values = parameter_default_values;
for (auto &conn : connections_)
new_mod->connect(conn);
const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
{
- return parameters.at(paramname);
+ const auto &it = parameters.find(paramname);
+ if (it != parameters.end())
+ return it->second;
+ if (module && module->design) {
+ RTLIL::Module *m = module->design->module(type);
+ if (m)
+ return m->parameter_default_values.at(paramname);
+ }
+ throw std::out_of_range("Cell::getParam()");
}
void RTLIL::Cell::sort()