#include "kernel/macc.h"
#include "kernel/celltypes.h"
#include "frontends/verilog/verilog_frontend.h"
+#include "frontends/verilog/preproc.h"
#include "backends/ilang/ilang_backend.h"
#include <string.h>
int RTLIL::IdString::last_created_idx_ptr_;
#endif
-IdString RTLIL::ID::A;
-IdString RTLIL::ID::B;
-IdString RTLIL::ID::Y;
-IdString RTLIL::ID::keep;
-IdString RTLIL::ID::whitebox;
-IdString RTLIL::ID::blackbox;
+#define X(_id) IdString RTLIL::ID::_id;
+#include "kernel/constids.inc"
+#undef X
+
dict<std::string, std::string> RTLIL::constpad;
+const pool<IdString> &RTLIL::builtin_ff_cell_types() {
+ static const pool<IdString> res = {
+ ID($sr),
+ ID($ff),
+ ID($dff),
+ ID($dffe),
+ ID($dffsr),
+ ID($adff),
+ ID($dlatch),
+ ID($dlatchsr),
+ ID($_DFFE_NN_),
+ ID($_DFFE_NP_),
+ ID($_DFFE_PN_),
+ ID($_DFFE_PP_),
+ ID($_DFFSR_NNN_),
+ ID($_DFFSR_NNP_),
+ ID($_DFFSR_NPN_),
+ ID($_DFFSR_NPP_),
+ ID($_DFFSR_PNN_),
+ ID($_DFFSR_PNP_),
+ ID($_DFFSR_PPN_),
+ ID($_DFFSR_PPP_),
+ ID($_DFF_NN0_),
+ ID($_DFF_NN1_),
+ ID($_DFF_NP0_),
+ ID($_DFF_NP1_),
+ ID($_DFF_N_),
+ ID($_DFF_PN0_),
+ ID($_DFF_PN1_),
+ ID($_DFF_PP0_),
+ ID($_DFF_PP1_),
+ ID($_DFF_P_),
+ ID($_DLATCHSR_NNN_),
+ ID($_DLATCHSR_NNP_),
+ ID($_DLATCHSR_NPN_),
+ ID($_DLATCHSR_NPP_),
+ ID($_DLATCHSR_PNN_),
+ ID($_DLATCHSR_PNP_),
+ ID($_DLATCHSR_PPN_),
+ ID($_DLATCHSR_PPP_),
+ ID($_DLATCH_N_),
+ ID($_DLATCH_P_),
+ ID($_FF_),
+ };
+ return res;
+}
+
RTLIL::Const::Const()
{
flags = RTLIL::CONST_FLAG_NONE;
return true;
}
+bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
+{
+ return attributes.count(id);
+}
+
void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
{
if (value)
return it->second.as_bool();
}
+void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
+{
+ if (value.empty())
+ attributes.erase(id);
+ else
+ attributes[id] = value;
+}
+
+string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
+{
+ std::string value;
+ const auto it = attributes.find(id);
+ if (it != attributes.end())
+ value = it->second.decode_string();
+ return value;
+}
+
void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
{
string attrval;
return data;
}
-void RTLIL::AttrObject::set_src_attribute(const std::string &src)
-{
- if (src.empty())
- attributes.erase(ID(src));
- else
- attributes[ID(src)] = src;
-}
-
-std::string RTLIL::AttrObject::get_src_attribute() const
-{
- std::string src;
- const auto it = attributes.find(ID(src));
- if (it != attributes.end())
- src = it->second.decode_string();
- return src;
-}
-
bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
{
if (full_selection)
}
RTLIL::Design::Design()
+ : verilog_defines (new define_map_t)
{
static unsigned int hashidx_count = 123456789;
hashidx_count = mkhash_xorshift(hashidx_count);
int module_count = 0;
for (auto mod : selected_modules()) {
- if (mod->get_bool_attribute(ID(top)))
+ if (mod->get_bool_attribute(ID::top))
return mod;
module_count++;
module = mod;
}
log_assert(modules_.at(module->name) == module);
+ log_assert(refcount_modules_ == 0);
modules_.erase(module->name);
delete module;
}
delete it->second;
processes.clear();
+ connections_.clear();
+
remove(delwires);
set_bool_attribute(ID::blackbox);
}
error(__LINE__);
if (check_matched_sign) {
- log_assert(expected_params.count(ID(A_SIGNED)) != 0 && expected_params.count(ID(B_SIGNED)) != 0);
- bool a_is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
- bool b_is_signed = cell->parameters.at(ID(B_SIGNED)).as_bool();
+ log_assert(expected_params.count(ID::A_SIGNED) != 0 && expected_params.count(ID::B_SIGNED) != 0);
+ bool a_is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
+ bool b_is_signed = cell->parameters.at(ID::B_SIGNED).as_bool();
if (a_is_signed != b_is_signed)
error(__LINE__);
}
return;
if (cell->type.in(ID($not), ID($pos), ID($neg))) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED), /*expected=*/false);
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED, /*expected=*/false);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type.in(ID($shift), ID($shiftx))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(cell->type != ID($pow));
return;
}
if (cell->type == ID($fa)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)));
- port(ID(C), param(ID(WIDTH)));
- port(ID(X), param(ID(WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH));
+ port(ID::C, param(ID::WIDTH));
+ port(ID::X, param(ID::WIDTH));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($lcu)) {
- port(ID(P), param(ID(WIDTH)));
- port(ID(G), param(ID(WIDTH)));
- port(ID(CI), 1);
- port(ID(CO), param(ID(WIDTH)));
+ port(ID::P, param(ID::WIDTH));
+ port(ID::G, param(ID::WIDTH));
+ port(ID::CI, 1);
+ port(ID::CO, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($alu)) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID(CI), 1);
- port(ID(BI), 1);
- port(ID(X), param(ID(Y_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
- port(ID(CO), param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::CI, 1);
+ port(ID::BI, 1);
+ port(ID::X, param(ID::Y_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
+ port(ID::CO, param(ID::Y_WIDTH));
check_expected(true);
return;
}
if (cell->type == ID($macc)) {
- param(ID(CONFIG));
- param(ID(CONFIG_WIDTH));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param(ID::CONFIG);
+ param(ID::CONFIG_WIDTH);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
Macc().from_cell(cell);
return;
}
if (cell->type == ID($logic_not)) {
- param_bool(ID(A_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($logic_and), ID($logic_or))) {
- param_bool(ID(A_SIGNED));
- param_bool(ID(B_SIGNED));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
+ param_bool(ID::A_SIGNED);
+ param_bool(ID::B_SIGNED);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
check_expected(/*check_matched_sign=*/false);
return;
}
if (cell->type == ID($slice)) {
- param(ID(OFFSET));
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::Y, param(ID(Y_WIDTH)));
- if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
+ param(ID::OFFSET);
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::Y, param(ID::Y_WIDTH));
+ if (param(ID::OFFSET) + param(ID::Y_WIDTH) > param(ID::A_WIDTH))
error(__LINE__);
check_expected();
return;
}
if (cell->type == ID($concat)) {
- port(ID::A, param(ID(A_WIDTH)));
- port(ID::B, param(ID(B_WIDTH)));
- port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
+ port(ID::A, param(ID::A_WIDTH));
+ port(ID::B, param(ID::B_WIDTH));
+ port(ID::Y, param(ID::A_WIDTH) + param(ID::B_WIDTH));
check_expected();
return;
}
if (cell->type == ID($mux)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)));
- port(ID(S), 1);
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH));
+ port(ID::S, 1);
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($pmux)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
- port(ID(S), param(ID(S_WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::A, param(ID::WIDTH));
+ port(ID::B, param(ID::WIDTH) * param(ID::S_WIDTH));
+ port(ID::S, param(ID::S_WIDTH));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($lut)) {
- param(ID(LUT));
- port(ID::A, param(ID(WIDTH)));
+ param(ID::LUT);
+ port(ID::A, param(ID::WIDTH));
port(ID::Y, 1);
check_expected();
return;
}
if (cell->type == ID($sop)) {
- param(ID(DEPTH));
- param(ID(TABLE));
- port(ID::A, param(ID(WIDTH)));
+ param(ID::DEPTH);
+ param(ID::TABLE);
+ port(ID::A, param(ID::WIDTH));
port(ID::Y, 1);
check_expected();
return;
}
if (cell->type == ID($sr)) {
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($ff)) {
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dff)) {
- param_bool(ID(CLK_POLARITY));
- port(ID(CLK), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dffe)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(EN_POLARITY));
- port(ID(CLK), 1);
- port(ID(EN), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::EN_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dffsr)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(CLK), 1);
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::CLK, 1);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($adff)) {
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(ARST_POLARITY));
- param_bits(ID(ARST_VALUE), param(ID(WIDTH)));
- port(ID(CLK), 1);
- port(ID(ARST), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param_bits(ID::ARST_VALUE, param(ID::WIDTH));
+ port(ID::CLK, 1);
+ port(ID::ARST, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dlatch)) {
- param_bool(ID(EN_POLARITY));
- port(ID(EN), 1);
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::EN_POLARITY);
+ port(ID::EN, 1);
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($dlatchsr)) {
- param_bool(ID(EN_POLARITY));
- param_bool(ID(SET_POLARITY));
- param_bool(ID(CLR_POLARITY));
- port(ID(EN), 1);
- port(ID(SET), param(ID(WIDTH)));
- port(ID(CLR), param(ID(WIDTH)));
- port(ID(D), param(ID(WIDTH)));
- port(ID(Q), param(ID(WIDTH)));
+ param_bool(ID::EN_POLARITY);
+ param_bool(ID::SET_POLARITY);
+ param_bool(ID::CLR_POLARITY);
+ port(ID::EN, 1);
+ port(ID::SET, param(ID::WIDTH));
+ port(ID::CLR, param(ID::WIDTH));
+ port(ID::D, param(ID::WIDTH));
+ port(ID::Q, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($fsm)) {
- param(ID(NAME));
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(ARST_POLARITY));
- param(ID(STATE_BITS));
- param(ID(STATE_NUM));
- param(ID(STATE_NUM_LOG2));
- param(ID(STATE_RST));
- param_bits(ID(STATE_TABLE), param(ID(STATE_BITS)) * param(ID(STATE_NUM)));
- param(ID(TRANS_NUM));
- param_bits(ID(TRANS_TABLE), param(ID(TRANS_NUM)) * (2*param(ID(STATE_NUM_LOG2)) + param(ID(CTRL_IN_WIDTH)) + param(ID(CTRL_OUT_WIDTH))));
- port(ID(CLK), 1);
- port(ID(ARST), 1);
- port(ID(CTRL_IN), param(ID(CTRL_IN_WIDTH)));
- port(ID(CTRL_OUT), param(ID(CTRL_OUT_WIDTH)));
+ param(ID::NAME);
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::ARST_POLARITY);
+ param(ID::STATE_BITS);
+ param(ID::STATE_NUM);
+ param(ID::STATE_NUM_LOG2);
+ param(ID::STATE_RST);
+ param_bits(ID::STATE_TABLE, param(ID::STATE_BITS) * param(ID::STATE_NUM));
+ param(ID::TRANS_NUM);
+ param_bits(ID::TRANS_TABLE, param(ID::TRANS_NUM) * (2*param(ID::STATE_NUM_LOG2) + param(ID::CTRL_IN_WIDTH) + param(ID::CTRL_OUT_WIDTH)));
+ port(ID::CLK, 1);
+ port(ID::ARST, 1);
+ port(ID::CTRL_IN, param(ID::CTRL_IN_WIDTH));
+ port(ID::CTRL_OUT, param(ID::CTRL_OUT_WIDTH));
check_expected();
return;
}
if (cell->type == ID($memrd)) {
- param(ID(MEMID));
- param_bool(ID(CLK_ENABLE));
- param_bool(ID(CLK_POLARITY));
- param_bool(ID(TRANSPARENT));
- port(ID(CLK), 1);
- port(ID(EN), 1);
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)));
+ param(ID::MEMID);
+ param_bool(ID::CLK_ENABLE);
+ param_bool(ID::CLK_POLARITY);
+ param_bool(ID::TRANSPARENT);
+ port(ID::CLK, 1);
+ port(ID::EN, 1);
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($memwr)) {
- param(ID(MEMID));
- param_bool(ID(CLK_ENABLE));
- param_bool(ID(CLK_POLARITY));
- param(ID(PRIORITY));
- port(ID(CLK), 1);
- port(ID(EN), param(ID(WIDTH)));
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)));
+ param(ID::MEMID);
+ param_bool(ID::CLK_ENABLE);
+ param_bool(ID::CLK_POLARITY);
+ param(ID::PRIORITY);
+ port(ID::CLK, 1);
+ port(ID::EN, param(ID::WIDTH));
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($meminit)) {
- param(ID(MEMID));
- param(ID(PRIORITY));
- port(ID(ADDR), param(ID(ABITS)));
- port(ID(DATA), param(ID(WIDTH)) * param(ID(WORDS)));
+ param(ID::MEMID);
+ param(ID::PRIORITY);
+ port(ID::ADDR, param(ID::ABITS));
+ port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS));
check_expected();
return;
}
if (cell->type == ID($mem)) {
- param(ID(MEMID));
- param(ID(SIZE));
- param(ID(OFFSET));
- param(ID(INIT));
- param_bits(ID(RD_CLK_ENABLE), max(1, param(ID(RD_PORTS))));
- param_bits(ID(RD_CLK_POLARITY), max(1, param(ID(RD_PORTS))));
- param_bits(ID(RD_TRANSPARENT), max(1, param(ID(RD_PORTS))));
- param_bits(ID(WR_CLK_ENABLE), max(1, param(ID(WR_PORTS))));
- param_bits(ID(WR_CLK_POLARITY), max(1, param(ID(WR_PORTS))));
- port(ID(RD_CLK), param(ID(RD_PORTS)));
- port(ID(RD_EN), param(ID(RD_PORTS)));
- port(ID(RD_ADDR), param(ID(RD_PORTS)) * param(ID(ABITS)));
- port(ID(RD_DATA), param(ID(RD_PORTS)) * param(ID(WIDTH)));
- port(ID(WR_CLK), param(ID(WR_PORTS)));
- port(ID(WR_EN), param(ID(WR_PORTS)) * param(ID(WIDTH)));
- port(ID(WR_ADDR), param(ID(WR_PORTS)) * param(ID(ABITS)));
- port(ID(WR_DATA), param(ID(WR_PORTS)) * param(ID(WIDTH)));
+ param(ID::MEMID);
+ param(ID::SIZE);
+ param(ID::OFFSET);
+ param(ID::INIT);
+ param_bits(ID::RD_CLK_ENABLE, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::RD_CLK_POLARITY, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::RD_TRANSPARENT, max(1, param(ID::RD_PORTS)));
+ param_bits(ID::WR_CLK_ENABLE, max(1, param(ID::WR_PORTS)));
+ param_bits(ID::WR_CLK_POLARITY, max(1, param(ID::WR_PORTS)));
+ port(ID::RD_CLK, param(ID::RD_PORTS));
+ port(ID::RD_EN, param(ID::RD_PORTS));
+ port(ID::RD_ADDR, param(ID::RD_PORTS) * param(ID::ABITS));
+ port(ID::RD_DATA, param(ID::RD_PORTS) * param(ID::WIDTH));
+ port(ID::WR_CLK, param(ID::WR_PORTS));
+ port(ID::WR_EN, param(ID::WR_PORTS) * param(ID::WIDTH));
+ port(ID::WR_ADDR, param(ID::WR_PORTS) * param(ID::ABITS));
+ port(ID::WR_DATA, param(ID::WR_PORTS) * param(ID::WIDTH));
check_expected();
return;
}
if (cell->type == ID($tribuf)) {
- port(ID::A, param(ID(WIDTH)));
- port(ID::Y, param(ID(WIDTH)));
- port(ID(EN), 1);
+ port(ID::A, param(ID::WIDTH));
+ port(ID::Y, param(ID::WIDTH));
+ port(ID::EN, 1);
check_expected();
return;
}
if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
port(ID::A, 1);
- port(ID(EN), 1);
+ port(ID::EN, 1);
check_expected();
return;
}
}
if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
- port(ID::Y, param(ID(WIDTH)));
+ port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
}
if (cell->type.in(ID($specify2), ID($specify3))) {
- param_bool(ID(FULL));
- param_bool(ID(SRC_DST_PEN));
- param_bool(ID(SRC_DST_POL));
- param(ID(T_RISE_MIN));
- param(ID(T_RISE_TYP));
- param(ID(T_RISE_MAX));
- param(ID(T_FALL_MIN));
- param(ID(T_FALL_TYP));
- param(ID(T_FALL_MAX));
- port(ID(EN), 1);
- port(ID(SRC), param(ID(SRC_WIDTH)));
- port(ID(DST), param(ID(DST_WIDTH)));
+ param_bool(ID::FULL);
+ param_bool(ID::SRC_DST_PEN);
+ param_bool(ID::SRC_DST_POL);
+ param(ID::T_RISE_MIN);
+ param(ID::T_RISE_TYP);
+ param(ID::T_RISE_MAX);
+ param(ID::T_FALL_MIN);
+ param(ID::T_FALL_TYP);
+ param(ID::T_FALL_MAX);
+ port(ID::EN, 1);
+ port(ID::SRC, param(ID::SRC_WIDTH));
+ port(ID::DST, param(ID::DST_WIDTH));
if (cell->type == ID($specify3)) {
- param_bool(ID(EDGE_EN));
- param_bool(ID(EDGE_POL));
- param_bool(ID(DAT_DST_PEN));
- param_bool(ID(DAT_DST_POL));
- port(ID(DAT), param(ID(DST_WIDTH)));
+ param_bool(ID::EDGE_EN);
+ param_bool(ID::EDGE_POL);
+ param_bool(ID::DAT_DST_PEN);
+ param_bool(ID::DAT_DST_POL);
+ port(ID::DAT, param(ID::DST_WIDTH));
}
check_expected();
return;
}
if (cell->type == ID($specrule)) {
- param(ID(TYPE));
- param_bool(ID(SRC_PEN));
- param_bool(ID(SRC_POL));
- param_bool(ID(DST_PEN));
- param_bool(ID(DST_POL));
- param(ID(T_LIMIT_MIN));
- param(ID(T_LIMIT_TYP));
- param(ID(T_LIMIT_MAX));
- param(ID(T_LIMIT2_MIN));
- param(ID(T_LIMIT2_TYP));
- param(ID(T_LIMIT2_MAX));
- port(ID(SRC_EN), 1);
- port(ID(DST_EN), 1);
- port(ID(SRC), param(ID(SRC_WIDTH)));
- port(ID(DST), param(ID(DST_WIDTH)));
+ param(ID::TYPE);
+ param_bool(ID::SRC_PEN);
+ param_bool(ID::SRC_POL);
+ param_bool(ID::DST_PEN);
+ param_bool(ID::DST_POL);
+ param(ID::T_LIMIT_MIN);
+ param(ID::T_LIMIT_TYP);
+ param(ID::T_LIMIT_MAX);
+ param(ID::T_LIMIT2_MIN);
+ param(ID::T_LIMIT2_TYP);
+ param(ID::T_LIMIT2_MAX);
+ port(ID::SRC_EN, 1);
+ port(ID::DST_EN, 1);
+ port(ID::SRC, param(ID::SRC_WIDTH));
+ port(ID::DST, param(ID::DST_WIDTH));
check_expected();
return;
}
if (cell->type == ID($_XNOR_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
if (cell->type == ID($_ANDNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
if (cell->type == ID($_ORNOT_)) { port(ID::A,1); port(ID::B,1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID(S),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID::Y,1); check_expected(); return; }
-
- if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID(E),1); check_expected(); return; }
-
- if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(S),1); port(ID(T),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID::Y,1); check_expected(); return; }
- if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID(C),1); port(ID(D),1); port(ID(E),1); port(ID(F),1); port(ID(G),1); port(ID(H),1); port(ID(I),1); port(ID(J),1); port(ID(K),1); port(ID(L),1); port(ID(M),1); port(ID(N),1); port(ID(O),1); port(ID(P),1); port(ID(S),1); port(ID(T),1); port(ID(U),1); port(ID(V),1); port(ID::Y,1); check_expected(); return; }
-
- if (cell->type == ID($_SR_NN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_NP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_PN_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_SR_PP_)) { port(ID(S),1); port(ID(R),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_FF_)) { port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFF_N_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
- if (cell->type == ID($_DFF_P_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); check_expected(); return; }
-
- if (cell->type == ID($_DFFE_NN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_NP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PN_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
- if (cell->type == ID($_DFFE_PP_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(E),1); check_expected(); return; }
-
- if (cell->type == ID($_DFF_NN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_NP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PN1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP0_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
- if (cell->type == ID($_DFF_PP1_)) { port(ID(D),1); port(ID(Q),1); port(ID(C),1); port(ID(R),1); check_expected(); return; }
-
- if (cell->type == ID($_DFFSR_NNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_NPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PNP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPN_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DFFSR_PPP_)) { port(ID(C),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCH_N_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCH_P_)) { port(ID(E),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
-
- if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
- if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID(E),1); port(ID(S),1); port(ID(R),1); port(ID(D),1); port(ID(Q),1); check_expected(); return; }
+ if (cell->type == ID($_MUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_NMUX_)) { port(ID::A,1); port(ID::B,1); port(ID::S,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_AOI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_OAI3_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_AOI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_OAI4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::Y,1); check_expected(); return; }
+
+ if (cell->type == ID($_TBUF_)) { port(ID::A,1); port(ID::Y,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type == ID($_MUX4_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::S,1); port(ID::T,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_MUX8_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::Y,1); check_expected(); return; }
+ if (cell->type == ID($_MUX16_)) { port(ID::A,1); port(ID::B,1); port(ID::C,1); port(ID::D,1); port(ID::E,1); port(ID::F,1); port(ID::G,1); port(ID::H,1); port(ID::I,1); port(ID::J,1); port(ID::K,1); port(ID::L,1); port(ID::M,1); port(ID::N,1); port(ID::O,1); port(ID::P,1); port(ID::S,1); port(ID::T,1); port(ID::U,1); port(ID::V,1); port(ID::Y,1); check_expected(); return; }
+
+ if (cell->type == ID($_SR_NN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_NP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_PN_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_SR_PP_)) { port(ID::S,1); port(ID::R,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_FF_)) { port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_N_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_P_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFFE_NN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_NP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_PN_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+ if (cell->type == ID($_DFFE_PP_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::E,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFF_NN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_NP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PN0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PN1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PP0_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+ if (cell->type == ID($_DFF_PP1_)) { port(ID::D,1); port(ID::Q,1); port(ID::C,1); port(ID::R,1); check_expected(); return; }
+
+ if (cell->type == ID($_DFFSR_NNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_NPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PNN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PNP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PPN_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DFFSR_PPP_)) { port(ID::C,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_DLATCH_N_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCH_P_)) { port(ID::E,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+
+ if (cell->type == ID($_DLATCHSR_NNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_NPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PNN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PNP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PPN_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
+ if (cell->type == ID($_DLATCHSR_PPP_)) { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
error(__LINE__);
}
{
wires_.sort(sort_by_id_str());
cells_.sort(sort_by_id_str());
- avail_parameters.sort(sort_by_id_str());
+ parameter_default_values.sort(sort_by_id_str());
memories.sort(sort_by_id_str());
processes.sort(sort_by_id_str());
for (auto &it : cells_)
log_assert(new_mod->refcount_cells_ == 0);
new_mod->avail_parameters = avail_parameters;
+ new_mod->parameter_default_values = parameter_default_values;
for (auto &conn : connections_)
new_mod->connect(conn);
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::Y, sig_y); \
cell->set_src_attribute(src); \
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(B_SIGNED)] = is_signed; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::B_SIGNED] = is_signed; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::B_WIDTH] = sig_b.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
cell->setPort(ID::Y, sig_y); \
#define DEF_METHOD(_func, _y_size, _type) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(A_SIGNED)] = is_signed; \
- cell->parameters[ID(B_SIGNED)] = false; \
- cell->parameters[ID(A_WIDTH)] = sig_a.size(); \
- cell->parameters[ID(B_WIDTH)] = sig_b.size(); \
- cell->parameters[ID(Y_WIDTH)] = sig_y.size(); \
+ cell->parameters[ID::A_SIGNED] = is_signed; \
+ cell->parameters[ID::B_SIGNED] = false; \
+ cell->parameters[ID::A_WIDTH] = sig_a.size(); \
+ cell->parameters[ID::B_WIDTH] = sig_b.size(); \
+ cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
cell->setPort(ID::Y, sig_y); \
#define DEF_METHOD(_func, _type, _pmux) \
RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
RTLIL::Cell *cell = addCell(name, _type); \
- cell->parameters[ID(WIDTH)] = sig_a.size(); \
- if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size(); \
+ cell->parameters[ID::WIDTH] = sig_a.size(); \
+ if (_pmux) cell->parameters[ID::S_WIDTH] = sig_s.size(); \
cell->setPort(ID::A, sig_a); \
cell->setPort(ID::B, sig_b); \
- cell->setPort(ID(S), sig_s); \
+ cell->setPort(ID::S, sig_s); \
cell->setPort(ID::Y, sig_y); \
cell->set_src_attribute(src); \
return cell; \
RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed, bool b_signed, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($pow));
- cell->parameters[ID(A_SIGNED)] = a_signed;
- cell->parameters[ID(B_SIGNED)] = b_signed;
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(B_WIDTH)] = sig_b.size();
- cell->parameters[ID(Y_WIDTH)] = sig_y.size();
+ cell->parameters[ID::A_SIGNED] = a_signed;
+ cell->parameters[ID::B_SIGNED] = b_signed;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::B_WIDTH] = sig_b.size();
+ cell->parameters[ID::Y_WIDTH] = sig_y.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
cell->setPort(ID::Y, sig_y);
RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($slice));
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(Y_WIDTH)] = sig_y.size();
- cell->parameters[ID(OFFSET)] = offset;
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::Y_WIDTH] = sig_y.size();
+ cell->parameters[ID::OFFSET] = offset;
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($concat));
- cell->parameters[ID(A_WIDTH)] = sig_a.size();
- cell->parameters[ID(B_WIDTH)] = sig_b.size();
+ cell->parameters[ID::A_WIDTH] = sig_a.size();
+ cell->parameters[ID::B_WIDTH] = sig_b.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
cell->setPort(ID::Y, sig_y);
RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($lut));
- cell->parameters[ID(LUT)] = lut;
- cell->parameters[ID(WIDTH)] = sig_a.size();
+ cell->parameters[ID::LUT] = lut;
+ cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($tribuf));
- cell->parameters[ID(WIDTH)] = sig_a.size();
+ cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
return cell;
{
RTLIL::Cell *cell = addCell(name, ID($assert));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($assume));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($live));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($fair));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::Cell *cell = addCell(name, ID($cover));
cell->setPort(ID::A, sig_a);
- cell->setPort(ID(EN), sig_en);
+ cell->setPort(ID::EN, sig_en);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($sr));
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($ff));
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dff));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffe(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dffe));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dffsr));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Const arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($adff));
- cell->parameters[ID(CLK_POLARITY)] = clk_polarity;
- cell->parameters[ID(ARST_POLARITY)] = arst_polarity;
- cell->parameters[ID(ARST_VALUE)] = arst_value;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(CLK), sig_clk);
- cell->setPort(ID(ARST), sig_arst);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::CLK_POLARITY] = clk_polarity;
+ cell->parameters[ID::ARST_POLARITY] = arst_polarity;
+ cell->parameters[ID::ARST_VALUE] = arst_value;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::CLK, sig_clk);
+ cell->setPort(ID::ARST, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDlatch(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dlatch));
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($dlatchsr));
- cell->parameters[ID(EN_POLARITY)] = en_polarity;
- cell->parameters[ID(SET_POLARITY)] = set_polarity;
- cell->parameters[ID(CLR_POLARITY)] = clr_polarity;
- cell->parameters[ID(WIDTH)] = sig_q.size();
- cell->setPort(ID(EN), sig_en);
- cell->setPort(ID(SET), sig_set);
- cell->setPort(ID(CLR), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->parameters[ID::EN_POLARITY] = en_polarity;
+ cell->parameters[ID::SET_POLARITY] = set_polarity;
+ cell->parameters[ID::CLR_POLARITY] = clr_polarity;
+ cell->parameters[ID::WIDTH] = sig_q.size();
+ cell->setPort(ID::EN, sig_en);
+ cell->setPort(ID::SET, sig_set);
+ cell->setPort(ID::CLR, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($_FF_));
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDffeGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
bool arst_value, bool clk_polarity, bool arst_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c%c%c_", clk_polarity ? 'P' : 'N', arst_polarity ? 'P' : 'N', arst_value ? '1' : '0'));
- cell->setPort(ID(C), sig_clk);
- cell->setPort(ID(R), sig_arst);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::C, sig_clk);
+ cell->setPort(ID::R, sig_arst);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::Cell* RTLIL::Module::addDlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCH_%c_", en_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity, bool set_polarity, bool clr_polarity, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, stringf("$_DLATCHSR_%c%c%c_", en_polarity ? 'P' : 'N', set_polarity ? 'P' : 'N', clr_polarity ? 'P' : 'N'));
- cell->setPort(ID(E), sig_en);
- cell->setPort(ID(S), sig_set);
- cell->setPort(ID(R), sig_clr);
- cell->setPort(ID(D), sig_d);
- cell->setPort(ID(Q), sig_q);
+ cell->setPort(ID::E, sig_en);
+ cell->setPort(ID::S, sig_set);
+ cell->setPort(ID::R, sig_clr);
+ cell->setPort(ID::D, sig_d);
+ cell->setPort(ID::Q, sig_q);
cell->set_src_attribute(src);
return cell;
}
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($anyconst));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($anyseq));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($allconst));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
{
RTLIL::SigSpec sig = addWire(NEW_ID, width);
Cell *cell = addCell(name, ID($allseq));
- cell->setParam(ID(WIDTH), width);
+ cell->setParam(ID::WIDTH, width);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
{
- return parameters.at(paramname);
+ const auto &it = parameters.find(paramname);
+ if (it != parameters.end())
+ return it->second;
+ if (module && module->design) {
+ RTLIL::Module *m = module->design->module(type);
+ if (m)
+ return m->parameter_default_values.at(paramname);
+ }
+ throw std::out_of_range("Cell::getParam()");
}
void RTLIL::Cell::sort()
return;
if (type == ID($mux) || type == ID($pmux)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
if (type == ID($pmux))
- parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
+ parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
check();
return;
}
if (type == ID($lut) || type == ID($sop)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::A]);
return;
}
if (type == ID($fa)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
return;
}
if (type == ID($lcu)) {
- parameters[ID(WIDTH)] = GetSize(connections_[ID(CO)]);
+ parameters[ID::WIDTH] = GetSize(connections_[ID::CO]);
return;
}
if (connections_.count(ID::A)) {
if (signedness_ab) {
if (set_a_signed)
- parameters[ID(A_SIGNED)] = true;
- else if (parameters.count(ID(A_SIGNED)) == 0)
- parameters[ID(A_SIGNED)] = false;
+ parameters[ID::A_SIGNED] = true;
+ else if (parameters.count(ID::A_SIGNED) == 0)
+ parameters[ID::A_SIGNED] = false;
}
- parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
+ parameters[ID::A_WIDTH] = GetSize(connections_[ID::A]);
}
if (connections_.count(ID::B)) {
if (signedness_ab) {
if (set_b_signed)
- parameters[ID(B_SIGNED)] = true;
- else if (parameters.count(ID(B_SIGNED)) == 0)
- parameters[ID(B_SIGNED)] = false;
+ parameters[ID::B_SIGNED] = true;
+ else if (parameters.count(ID::B_SIGNED) == 0)
+ parameters[ID::B_SIGNED] = false;
}
- parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
+ parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
}
if (connections_.count(ID::Y))
- parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
+ parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
- if (connections_.count(ID(Q)))
- parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
+ if (connections_.count(ID::Q))
+ parameters[ID::WIDTH] = GetSize(connections_[ID::Q]);
check();
}
projects / yosys.git / blobdiff