kernel/yosys.h: undef CONST on WIN32

[yosys.git] / kernel / rtlil.cc

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d7d2269422b8a2bb3addc5145fd5ce34560d9976..1faf376e7fd67fc1c3822c4afcdd5924b96dd3c8 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -22,7 +22,7 @@
 #include "kernel/celltypes.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "frontends/verilog/preproc.h"
-#include "backends/ilang/ilang_backend.h"
+#include "backends/rtlil/rtlil_backend.h"
 
 #include <string.h>
 #include <algorithm>
@@ -923,7 +923,7 @@ namespace {
                void error(int linenr)
                {
                        std::stringstream buf;
-                       ILANG_BACKEND::dump_cell(buf, "  ", cell);
+                       RTLIL_BACKEND::dump_cell(buf, "  ", cell);
 
                        log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s",
                                        module ? module->name.c_str() : "", module ? "." : "",
@@ -1035,7 +1035,11 @@ namespace {
                        }
 
                        if (cell->type.in(ID($shift), ID($shiftx))) {
-                               param_bool(ID::A_SIGNED);
+                               if (cell->type == ID($shiftx)) {
+                                       param_bool(ID::A_SIGNED, /*expected=*/false);
+                               } else {
+                                       param_bool(ID::A_SIGNED);
+                               }
                                param_bool(ID::B_SIGNED);
                                port(ID::A, param(ID::A_WIDTH));
                                port(ID::B, param(ID::B_WIDTH));
@@ -1822,7 +1826,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
                        sig.pack();
                        for (auto &c : sig.chunks_)
                                if (c.wire != NULL && wires_p->count(c.wire)) {
-                                       c.wire = module->addWire(NEW_ID, c.width);
+                                       c.wire = module->addWire(stringf("$delete_wire$%d", autoidx++), c.width);
                                        c.offset = 0;
                                }
                }