Remember global declarations and defines accross read_verilog calls

[yosys.git] / kernel / rtlil.cc

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 66bbf0427bb01e4c3db41541d53d767e5147f3e6..7693e3052105525f51c5522257214532729a351e 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -306,6 +306,8 @@ RTLIL::Design::~Design()
                delete it->second;
        for (auto n : verilog_packages)
                delete n;
+       for (auto n : verilog_globals)
+               delete n;
 }
 
 RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()