Fix leak removing cells during ABC integration; also preserve attr

[yosys.git] / kernel / rtlil.h

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f4fcf5dcfb6e2c4fe8928f98c5b93fceb293818a..4a0f8b4f86910b202f3bb564a6b39bafcf9d54f5 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1040,6 +1040,7 @@ public:
        // Removing wires is expensive. If you have to remove wires, remove them all at once.
        void remove(const pool<RTLIL::Wire*> &wires);
        void remove(RTLIL::Cell *cell);
+       dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it);
 
        void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
        void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);