Move muxpack from passes/techmap to passes/opt

[yosys.git] / kernel / rtlil.h

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 176dc3fc2d5940d8e3e5f885592c4e9f6eafa43b..8509670ff4b2580361c8cb3a01555a718a01e441 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -50,7 +50,7 @@ namespace RTLIL
                CONST_FLAG_NONE   = 0,
                CONST_FLAG_STRING = 1,
                CONST_FLAG_SIGNED = 2,  // only used for parameters
-               CONST_FLAG_REAL   = 4   // unused -- to be used for parameters
+               CONST_FLAG_REAL   = 4   // only used for parameters
        };
 
        struct Const;
@@ -517,6 +517,8 @@ struct RTLIL::Const
        Const(RTLIL::State bit, int width = 1);
        Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; }
        Const(const std::vector<bool> &bits);
+       Const(const RTLIL::Const &c);
+       RTLIL::Const &operator =(const RTLIL::Const &other) = default;
 
        bool operator <(const RTLIL::Const &other) const;
        bool operator ==(const RTLIL::Const &other) const;
@@ -566,11 +568,11 @@ struct RTLIL::AttrObject
 {
        dict<RTLIL::IdString, RTLIL::Const> attributes;
 
-       void set_bool_attribute(RTLIL::IdString id);
+       void set_bool_attribute(RTLIL::IdString id, bool value=true);
        bool get_bool_attribute(RTLIL::IdString id) const;
 
-       bool get_blackbox_attribute() const {
-               return get_bool_attribute("\\blackbox") || get_bool_attribute("\\whitebox");
+       bool get_blackbox_attribute(bool ignore_wb=false) const {
+               return get_bool_attribute("\\blackbox") || (!ignore_wb && get_bool_attribute("\\whitebox"));
        }
 
        void set_strpool_attribute(RTLIL::IdString id, const pool<string> &data);
@@ -595,8 +597,11 @@ struct RTLIL::SigChunk
        SigChunk(int val, int width = 32);
        SigChunk(RTLIL::State bit, int width = 1);
        SigChunk(RTLIL::SigBit bit);
+       SigChunk(const RTLIL::SigChunk &sigchunk);
+       RTLIL::SigChunk &operator =(const RTLIL::SigChunk &other) = default;
 
        RTLIL::SigChunk extract(int offset, int length) const;
+       inline int size() const { return width; }
 
        bool operator <(const RTLIL::SigChunk &other) const;
        bool operator ==(const RTLIL::SigChunk &other) const;
@@ -619,6 +624,8 @@ struct RTLIL::SigBit
        SigBit(const RTLIL::SigChunk &chunk);
        SigBit(const RTLIL::SigChunk &chunk, int index);
        SigBit(const RTLIL::SigSpec &sig);
+       SigBit(const RTLIL::SigBit &sigbit);
+       RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
 
        bool operator <(const RTLIL::SigBit &other) const;
        bool operator ==(const RTLIL::SigBit &other) const;
@@ -940,9 +947,13 @@ struct RTLIL::Design
                }
        }
 
+
        std::vector<RTLIL::Module*> selected_modules() const;
        std::vector<RTLIL::Module*> selected_whole_modules() const;
        std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
+#ifdef WITH_PYTHON
+       static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
+#endif
 };
 
 struct RTLIL::Module : public RTLIL::AttrObject
@@ -991,6 +1002,7 @@ public:
        void fixup_ports();
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        void cloneInto(RTLIL::Module *new_mod) const;
        virtual RTLIL::Module *clone() const;
 
@@ -1199,6 +1211,10 @@ public:
        RTLIL::SigSpec Allconst  (RTLIL::IdString name, int width = 1, const std::string &src = "");
        RTLIL::SigSpec Allseq    (RTLIL::IdString name, int width = 1, const std::string &src = "");
        RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
+
+#ifdef WITH_PYTHON
+       static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
+#endif
 };
 
 struct RTLIL::Wire : public RTLIL::AttrObject
@@ -1210,7 +1226,7 @@ protected:
        // use module->addWire() and module->remove() to create or destroy wires
        friend struct RTLIL::Module;
        Wire();
-       ~Wire() { };
+       ~Wire();
 
 public:
        // do not simply copy wires
@@ -1221,6 +1237,10 @@ public:
        RTLIL::IdString name;
        int width, start_offset, port_id;
        bool port_input, port_output, upto;
+
+#ifdef WITH_PYTHON
+       static std::map<unsigned int, RTLIL::Wire*> *get_all_wires(void);
+#endif
 };
 
 struct RTLIL::Memory : public RTLIL::AttrObject
@@ -1232,6 +1252,10 @@ struct RTLIL::Memory : public RTLIL::AttrObject
 
        RTLIL::IdString name;
        int width, start_offset, size;
+#ifdef WITH_PYTHON
+       ~Memory();
+       static std::map<unsigned int, RTLIL::Memory*> *get_all_memorys(void);
+#endif
 };
 
 struct RTLIL::Cell : public RTLIL::AttrObject
@@ -1243,6 +1267,7 @@ protected:
        // use module->addCell() and module->remove() to create or destroy cells
        friend struct RTLIL::Module;
        Cell();
+       ~Cell();
 
 public:
        // do not simply copy cells
@@ -1283,6 +1308,11 @@ public:
        }
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
+
+#ifdef WITH_PYTHON
+       static std::map<unsigned int, RTLIL::Cell*> *get_all_cells(void);
+#endif
 };
 
 struct RTLIL::CaseRule
@@ -1297,6 +1327,7 @@ struct RTLIL::CaseRule
        bool empty() const;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::CaseRule *clone() const;
 };
 
@@ -1310,6 +1341,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
        bool empty() const;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::SwitchRule *clone() const;
 };
 
@@ -1320,6 +1352,7 @@ struct RTLIL::SyncRule
        std::vector<RTLIL::SigSig> actions;
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::SyncRule *clone() const;
 };
 
@@ -1332,6 +1365,7 @@ struct RTLIL::Process : public RTLIL::AttrObject
        ~Process();
 
        template<typename T> void rewrite_sigspecs(T &functor);
+       template<typename T> void rewrite_sigspecs2(T &functor);
        RTLIL::Process *clone() const;
 };
 
@@ -1343,6 +1377,7 @@ inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_as
 inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
 inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
+inline RTLIL::SigBit::SigBit(const RTLIL::SigBit &sigbit) : wire(sigbit.wire), data(sigbit.data){if(wire) offset = sigbit.offset;}
 
 inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
        if (wire == other.wire)
@@ -1392,12 +1427,30 @@ void RTLIL::Module::rewrite_sigspecs(T &functor)
        }
 }
 
+template<typename T>
+void RTLIL::Module::rewrite_sigspecs2(T &functor)
+{
+       for (auto &it : cells_)
+               it.second->rewrite_sigspecs2(functor);
+       for (auto &it : processes)
+               it.second->rewrite_sigspecs2(functor);
+       for (auto &it : connections_) {
+               functor(it.first, it.second);
+       }
+}
+
 template<typename T>
 void RTLIL::Cell::rewrite_sigspecs(T &functor) {
        for (auto &it : connections_)
                functor(it.second);
 }
 
+template<typename T>
+void RTLIL::Cell::rewrite_sigspecs2(T &functor) {
+       for (auto &it : connections_)
+               functor(it.second);
+}
+
 template<typename T>
 void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
        for (auto &it : compare)
@@ -1410,6 +1463,17 @@ void RTLIL::CaseRule::rewrite_sigspecs(T &functor) {
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::CaseRule::rewrite_sigspecs2(T &functor) {
+       for (auto &it : compare)
+               functor(it);
+       for (auto &it : actions) {
+               functor(it.first, it.second);
+       }
+       for (auto it : switches)
+               it->rewrite_sigspecs2(functor);
+}
+
 template<typename T>
 void RTLIL::SwitchRule::rewrite_sigspecs(T &functor)
 {
@@ -1418,6 +1482,14 @@ void RTLIL::SwitchRule::rewrite_sigspecs(T &functor)
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::SwitchRule::rewrite_sigspecs2(T &functor)
+{
+       functor(signal);
+       for (auto it : cases)
+               it->rewrite_sigspecs2(functor);
+}
+
 template<typename T>
 void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
 {
@@ -1428,6 +1500,15 @@ void RTLIL::SyncRule::rewrite_sigspecs(T &functor)
        }
 }
 
+template<typename T>
+void RTLIL::SyncRule::rewrite_sigspecs2(T &functor)
+{
+       functor(signal);
+       for (auto &it : actions) {
+               functor(it.first, it.second);
+       }
+}
+
 template<typename T>
 void RTLIL::Process::rewrite_sigspecs(T &functor)
 {
@@ -1436,6 +1517,14 @@ void RTLIL::Process::rewrite_sigspecs(T &functor)
                it->rewrite_sigspecs(functor);
 }
 
+template<typename T>
+void RTLIL::Process::rewrite_sigspecs2(T &functor)
+{
+       root_case.rewrite_sigspecs2(functor);
+       for (auto it : syncs)
+               it->rewrite_sigspecs2(functor);
+}
+
 YOSYS_NAMESPACE_END
 
 #endif