Remember global declarations and defines accross read_verilog calls

[yosys.git] / kernel / rtlil.h

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 9430dcb3668db1b76d3ea6a16abd3f53efcfc582..8dd8fcca3aae341113ac0715bfe87f8e51e2f2d4 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -793,7 +793,8 @@ struct RTLIL::Design
 
        int refcount_modules_;
        dict<RTLIL::IdString, RTLIL::Module*> modules_;
-       std::vector<AST::AstNode*> verilog_packages;
+       std::vector<AST::AstNode*> verilog_packages, verilog_globals;
+       dict<std::string, std::pair<std::string, bool>> verilog_defines;
 
        std::vector<RTLIL::Selection> selection_stack;
        dict<RTLIL::IdString, RTLIL::Selection> selection_vars;