void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
{
bool is_signed = forced_signed;
- if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0)
- is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
+ if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)
+ is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
{
- bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool());
+ bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());
while (vec_a.size() < vec_y.size())
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_y.size() < vec_a.size())
if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod)) || is_arith_compare))
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
if (is_arith_compare)
extendSignalWidth(undef_a, undef_b, cell, true);
else
int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
if (cell->type.in(ID($div), ID($mod))) {
- std::vector<int> b = importSigSpec(cell->getPort(ID(B)), timestep);
+ std::vector<int> b = importSigSpec(cell->getPort(ID::B), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
}
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && !arith_undef_handled)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) {
}
else if (model_undef)
{
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_));
bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_));
- int a = importDefSigSpec(cell->getPort(ID(A)), timestep).at(0);
- int b = importDefSigSpec(cell->getPort(ID(B)), timestep).at(0);
- int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0);
- int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0);
- int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+ int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
+ int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
+ int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
+ int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
+ int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int yy = model_undef ? ez->literal() : y;
if (cell->type.in(ID($_AOI3_), ID($_AOI4_)))
if (model_undef)
{
- int undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep).at(0);
- int undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep).at(0);
- int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0);
- int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0);
- int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+ int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
+ int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
+ int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
+ int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
+ int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
if (aoi_mode)
{
if (cell->type.in(ID($_NOT_), ID($not)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(ez->vec_not(a), yy));
if (model_undef) {
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (cell->type == ID($_NMUX_))
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
if (cell->type == ID($pmux))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
int maybe_a = ez->CONST_TRUE;
if (cell->type.in(ID($pos), ID($neg)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell);
if (cell->type == ID($pos)) {
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
int aX = ez->expression(ezSAT::OpOr, undef_a);
if (cell->type == ID($reduce_and)) {
if (cell->type.in(ID($logic_and), ID($logic_or)))
{
- std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep);
+ std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID::B), timestep);
int a = ez->expression(ez->OpOr, vec_a);
int b = ez->expression(ez->OpOr, vec_b);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{
- bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(a, b, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
a = ez->vec_or(a, undef_a);
b = ez->vec_or(b, undef_b);
if (model_undef && cell->type.in(ID($eqx), ID($nex)))
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
if (cell->type == ID($eqx))
}
else if (model_undef && cell->type.in(ID($eq), ID($ne)))
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
else
{
if (model_undef) {
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undefGating(y, yy, undef_y);
}
log_assert(!model_undef || arith_undef_handled);
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
int extend_bit = ez->CONST_FALSE;
- if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
+ if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = a.back();
while (y.size() < a.size())
shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr))
- shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
+ shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type.in(ID($shift), ID($shiftx)))
- shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
+ shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
ez->assume(ez->vec_eq(shifted_a, yy));
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a_shifted;
extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
- if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
+ if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = undef_a.back();
while (undef_y.size() < undef_a.size())
undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shift))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shiftx))
- undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
+ undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
if (cell->type == ID($mul))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef) {
log_assert(arith_undef_handled);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
if (cell->type == ID($macc))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
Macc macc;
macc.from_cell(cell);
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), ez->OR(undef_any_a, undef_any_b))));
undefGating(y, tmp, undef_y);
if (cell->type.in(ID($div), ID($mod)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> a_u, b_u;
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
} else {
std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
if (cell->type == ID($div)) {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
else
ez->assume(ez->vec_eq(y_tmp, y_u));
} else {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
else
ez->assume(ez->vec_eq(y_tmp, chain_buf));
} else {
std::vector<int> div_zero_result;
if (cell->type == ID($div)) {
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
only_first_one.at(0) = ez->CONST_TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
- div_zero_result.insert(div_zero_result.end(), cell->getPort(ID(A)).size(), ez->CONST_TRUE);
+ div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
} else {
- int copy_a_bits = min(cell->getPort(ID(A)).size(), cell->getPort(ID(B)).size());
+ int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
- if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
+ if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
else
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
if (model_undef) {
log_assert(arith_undef_handled);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
if (cell->type == ID($lut))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> lut;
- for (auto bit : cell->getParam(ID(LUT)).bits)
+ for (auto bit : cell->getParam(ID::LUT).bits)
lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->CONST_FALSE);
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> t(lut), u(GetSize(t), ez->CONST_FALSE);
for (int i = GetSize(a)-1; i >= 0; i--)
log_assert(GetSize(t) == 1);
log_assert(GetSize(u) == 1);
undefGating(y, t, u);
- ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID(Y)), timestep), u));
+ ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u));
}
else
{
if (cell->type == ID($sop))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
- int width = cell->getParam(ID(WIDTH)).as_int();
- int depth = cell->getParam(ID(DEPTH)).as_int();
+ int width = cell->getParam(ID::WIDTH).as_int();
+ int depth = cell->getParam(ID::DEPTH).as_int();
- vector<State> table_raw = cell->getParam(ID(TABLE)).bits;
+ vector<State> table_raw = cell->getParam(ID::TABLE).bits;
while (GetSize(table_raw) < 2*width*depth)
table_raw.push_back(State::S0);
if (model_undef)
{
std::vector<int> products, undef_products;
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
for (int i = 0; i < depth; i++)
{
if (cell->type == ID($fa))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
- std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
+ std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
- std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
+ std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y));
if (cell->type == ID($lcu))
{
- std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep);
- std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep);
- std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
+ std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
+ std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
if (model_undef)
{
- std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep);
- std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep);
- std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
+ std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
+ std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
if (cell->type == ID($alu))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
- std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
- std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep);
- std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
+ std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
+ std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
+ std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(a, b, y, cell);
extendSignalWidth(a, b, x, cell);
if (model_undef)
{
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
- std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
- std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+ std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
+ std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
- std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
- std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
+ std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
+ std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell);
if (cell->type == ID($slice))
{
- RTLIL::SigSpec a = cell->getPort(ID(A));
- RTLIL::SigSpec y = cell->getPort(ID(Y));
- ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep));
+ RTLIL::SigSpec a = cell->getPort(ID::A);
+ RTLIL::SigSpec y = cell->getPort(ID::Y);
+ ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
return true;
}
if (cell->type == ID($concat))
{
- RTLIL::SigSpec a = cell->getPort(ID(A));
- RTLIL::SigSpec b = cell->getPort(ID(B));
- RTLIL::SigSpec y = cell->getPort(ID(Y));
+ RTLIL::SigSpec a = cell->getPort(ID::A);
+ RTLIL::SigSpec b = cell->getPort(ID::B);
+ RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec ab = a;
ab.append(b);
{
if (timestep == 1)
{
- initial_state.add((*sigmap)(cell->getPort(ID(Q))));
+ initial_state.add((*sigmap)(cell->getPort(ID::Q)));
}
else
{
- std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1);
- std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep);
+ std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
+ std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
- std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1);
- std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep);
+ std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
+ std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
if (timestep < 2)
return true;
- std::vector<int> d = importDefSigSpec(cell->getPort(ID(Y)), timestep-1);
- std::vector<int> q = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> d = importDefSigSpec(cell->getPort(ID::Y), timestep-1);
+ std::vector<int> q = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
- std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(Y)), timestep-1);
- std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1);
+ std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
if (cell->type.in(ID($_BUF_), ID($equiv)))
{
- std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(a, yy));
if (model_undef) {
- std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
if (initstates.count(key) == 0)
initstates[key] = false;
- std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
log_assert(GetSize(y) == 1);
ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE);
if (model_undef) {
- std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+ std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
log_assert(GetSize(undef_y) == 1);
ez->SET(undef_y[0], ez->CONST_FALSE);
}
if (cell->type == ID($assert))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
- asserts_a[pf].append((*sigmap)(cell->getPort(ID(A))));
- asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
+ asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
+ asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true;
}
if (cell->type == ID($assume))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
- assumes_a[pf].append((*sigmap)(cell->getPort(ID(A))));
- assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
+ assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
+ assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true;
}
projects / yosys.git / blobdiff