ice40: split out cells_map.v into ff_map.v

[yosys.git] / kernel / timinginfo.h

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index 7855ddd15db858db88cd77c6997dda7df47513ad..fb4e0930d7128f3a9f0e5678eb5bdb11998cd111 100644 (file)
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -18,8 +18,8 @@
  *
  */
 
-#ifndef TIMINGARCS_H
-#define TIMINGARCS_H
+#ifndef TIMINGINFO_H
+#define TIMINGINFO_H
 
 #include "kernel/yosys.h"
 
@@ -38,7 +38,14 @@ struct TimingInfo
                bool operator!=(const NameBit& nb) const { return !operator==(nb); }
                unsigned int hash() const { return mkhash_add(name.hash(), offset); }
        };
-       typedef std::pair<NameBit,NameBit> BitBit;
+       struct BitBit
+       {
+               NameBit first, second;
+               BitBit(const NameBit &first, const NameBit &second) : first(first), second(second) {}
+               BitBit(const SigBit &first, const SigBit &second) : first(first), second(second) {}
+               bool operator==(const BitBit& bb) const { return bb.first == first && bb.second == second; }
+               unsigned int hash() const { return mkhash_add(first.hash(), second.hash()); }
+       };
 
        struct ModuleTiming
        {
@@ -75,20 +82,20 @@ struct TimingInfo
 
                for (auto cell : module->cells()) {
                        if (cell->type == ID($specify2)) {
-                               auto src = cell->getPort(ID(SRC));
-                               auto dst = cell->getPort(ID(DST));
+                               auto src = cell->getPort(ID::SRC);
+                               auto dst = cell->getPort(ID::DST);
                                for (const auto &c : src.chunks())
                                        if (!c.wire->port_input)
                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
                                for (const auto &c : dst.chunks())
                                        if (!c.wire->port_output)
                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-                               int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-                               int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+                               int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
+                               int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
                                int max = std::max(rise_max,fall_max);
                                if (max < 0)
                                        log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
-                               if (cell->getParam(ID(FULL)).as_bool()) {
+                               if (cell->getParam(ID::FULL).as_bool()) {
                                        for (const auto &s : src)
                                                for (const auto &d : dst) {
                                                        auto r = t.comb.insert(BitBit(s,d));
@@ -110,16 +117,16 @@ struct TimingInfo
                                }
                        }
                        else if (cell->type == ID($specify3)) {
-                               auto src = cell->getPort(ID(SRC));
-                               auto dst = cell->getPort(ID(DST));
+                               auto src = cell->getPort(ID::SRC);
+                               auto dst = cell->getPort(ID::DST);
                                for (const auto &c : src.chunks())
                                        if (!c.wire->port_input)
                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
                                for (const auto &c : dst.chunks())
                                        if (!c.wire->port_output)
                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
-                               int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int();
-                               int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int();
+                               int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
+                               int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
                                int max = std::max(rise_max,fall_max);
                                if (max < 0)
                                        log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
@@ -133,18 +140,18 @@ struct TimingInfo
                                }
                        }
                        else if (cell->type == ID($specrule)) {
-                               auto type = cell->getParam(ID(TYPE)).decode_string();
+                               auto type = cell->getParam(ID::TYPE).decode_string();
                                if (type != "$setup" && type != "$setuphold")
                                        continue;
-                               auto src = cell->getPort(ID(SRC));
-                               auto dst = cell->getPort(ID(DST));
+                               auto src = cell->getPort(ID::SRC);
+                               auto dst = cell->getPort(ID::DST);
                                for (const auto &c : src.chunks())
                                        if (!c.wire->port_input)
                                                log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
                                for (const auto &c : dst.chunks())
                                        if (!c.wire->port_input)
                                                log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
-                               int max = cell->getParam(ID(T_LIMIT_MAX)).as_int();
+                               int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
                                if (max < 0)
                                        log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
                                if (max <= 0) {