Merge pull request #1845 from YosysHQ/eddie/kernel_speedup

[yosys.git] / kernel / yosys.cc

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 5a53f90fddabf71a9098559307a6689ea61bd2c0..6d64e2e90133729159aae0200969b5a6d5263972 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -129,7 +129,7 @@ void yosys_banner()
        log(" |                                                                            |\n");
        log(" |  yosys -- Yosys Open SYnthesis Suite                                       |\n");
        log(" |                                                                            |\n");
-       log(" |  Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>           |\n");
+       log(" |  Copyright (C) 2012 - 2020  Claire Wolf <claire@symbioticeda.com>          |\n");
        log(" |                                                                            |\n");
        log(" |  Permission to use, copy, modify, and/or distribute this software for any  |\n");
        log(" |  purpose with or without fee is hereby granted, provided that the above    |\n");
@@ -341,7 +341,11 @@ int run_command(const std::string &command, std::function<void(const std::string
        if (!process_line)
                return system(command.c_str());
 
+#ifdef EMSCRIPTEN
+       FILE *f = nullptr;
+#else
        FILE *f = popen(command.c_str(), "r");
+#endif
        if (f == nullptr)
                return -1;
 
@@ -510,10 +514,13 @@ void yosys_setup()
        if(already_setup)
                return;
        already_setup = true;
-       // if there are already IdString objects then we have a global initialization order bug
-       IdString empty_id;
-       log_assert(empty_id.index_ == 0);
-       IdString::get_reference(empty_id.index_);
+
+       RTLIL::ID::A = "\\A";
+       RTLIL::ID::B = "\\B";
+       RTLIL::ID::Y = "\\Y";
+       RTLIL::ID::keep = "\\keep";
+       RTLIL::ID::whitebox = "\\whitebox";
+       RTLIL::ID::blackbox = "\\blackbox";
 
        #ifdef WITH_PYTHON
                PyImport_AppendInittab((char*)"libyosys", INIT_MODULE);
@@ -541,6 +548,8 @@ void yosys_shutdown()
        already_shutdown = true;
        log_pop();
 
+       Pass::done_register();
+
        delete yosys_design;
        yosys_design = NULL;
 
@@ -550,7 +559,6 @@ void yosys_shutdown()
        log_errfile = NULL;
        log_files.clear();
 
-       Pass::done_register();
        yosys_celltypes.clear();
 
 #ifdef YOSYS_ENABLE_TCL
@@ -575,9 +583,6 @@ void yosys_shutdown()
 #ifdef WITH_PYTHON
        Py_Finalize();
 #endif
-
-       IdString empty_id;
-       IdString::put_reference(empty_id.index_);
 }
 
 RTLIL::IdString new_id(std::string file, int line, std::string func)
@@ -1093,30 +1098,29 @@ static char *readline_obj_generator(const char *text, int state)
 
                if (design->selected_active_module.empty())
                {
-                       for (auto &it : design->modules_)
-                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
-                                       obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
+                       for (auto mod : design->modules())
+                               if (RTLIL::unescape_id(mod->name).compare(0, len, text) == 0)
+                                       obj_names.push_back(strdup(log_id(mod->name)));
                }
-               else
-               if (design->modules_.count(design->selected_active_module) > 0)
+               else if (design->module(design->selected_active_module) != nullptr)
                {
-                       RTLIL::Module *module = design->modules_.at(design->selected_active_module);
+                       RTLIL::Module *module = design->module(design->selected_active_module);
 
-                       for (auto &it : module->wires_)
-                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
-                                       obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
+                       for (auto w : module->wires())
+                               if (RTLIL::unescape_id(w->name).compare(0, len, text) == 0)
+                                       obj_names.push_back(strdup(log_id(w->name)));
 
                        for (auto &it : module->memories)
                                if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
-                                       obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
+                                       obj_names.push_back(strdup(log_id(it.first)));
 
-                       for (auto &it : module->cells_)
-                               if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
-                                       obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
+                       for (auto cell : module->cells())
+                               if (RTLIL::unescape_id(cell->name).compare(0, len, text) == 0)
+                                       obj_names.push_back(strdup(log_id(cell->name)));
 
                        for (auto &it : module->processes)
                                if (RTLIL::unescape_id(it.first).compare(0, len, text) == 0)
-                                       obj_names.push_back(strdup(RTLIL::id2cstr(it.first)));
+                                       obj_names.push_back(strdup(log_id(it.first)));
                }
 
                std::sort(obj_names.begin(), obj_names.end());