rename hyperram clk pads to "ck"

[lambdasoc.git] / lambdasoc / periph / hyperram.py

diff --git a/lambdasoc/periph/hyperram.py b/lambdasoc/periph/hyperram.py
index 8284ef3efe3aa0c5aedf286dc81eca20ccae4aa3..e0d54bd7e694bb743b9453ddcf17af1af975f9c0 100644 (file)
--- a/lambdasoc/periph/hyperram.py
+++ b/lambdasoc/periph/hyperram.py
@@ -18,7 +18,7 @@ use platform.add_extension to first define the pins:
     from nmigen.resources.memory import HyperRAMResources
     hyperram_ios = HyperRAMResources(cs_n="B1",
                                      dq="D0 D1 D2 D3 D4 D7 D6 D7",
-                                     rwds="B2", rst_n="B3", clk_p="B4",
+                                     rwds="B2", rst_n="B3", ck_p="B4",
                                      attrs=IOStandard("LVCMOS33"))
     self.platform.add_extension(hyperram_ios)
     io = self.platform.request("hyperram")
@@ -45,7 +45,7 @@ from lambdasoc.periph import Peripheral
 class HyperRAMASICPhy(Elaboratable):
     def __init__(self, io):
         self.io = io
-        self.clk = clk = Signal()
+        self.ck = ck = Signal()
         self.cs  = cs = Signal()
 
         self.dq_o  = dq_o  = Signal(8)
@@ -58,7 +58,7 @@ class HyperRAMASICPhy(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
-        clk, cs = self.clk, self.cs
+        ck, cs = self.ck, self.cs
         dq_o, dq_i, dq_oe = self.dq_o, self.dq_i, self.dq_oe
         rwds_o, rwds_oe = self.rwds_o, self.rwds_oe
 
@@ -66,8 +66,8 @@ class HyperRAMASICPhy(Elaboratable):
             self.io["rwds_o"].eq(rwds_o),
             self.io["csn_o"].eq(~cs),
             self.io["csn_oe"].eq(0),
-            self.io["clk_o"].eq(clk),
-            self.io["clk_oe"].eq(0),
+            self.io["ck_o"].eq(ck),
+            self.io["ck_oe"].eq(0),
             self.io["rwds_oe"].eq(~rwds_oe),
         ]
 
@@ -90,7 +90,7 @@ class HyperRAMASICPhy(Elaboratable):
 
 class HyperRAMPads:
     def __init__(self, dw=8):
-        self.clk  = Signal()
+        self.ck  = Signal()
         self.cs_n = Signal()
         self.dq   = Record([("oe", 1), ("o", dw),     ("i", dw)])
         self.rwds = Record([("oe", 1), ("o", dw//8),  ("i", dw//8)])
@@ -99,7 +99,7 @@ class HyperRAMPads:
 class HyperRAMPHY(Elaboratable):
     def __init__(self, pads):
         self.pads = pads
-        self.clk = pads.clk
+        self.ck = pads.ck
         self.cs = Signal()
         self.dq_o = pads.dq.o
         self.dq_i = pads.dq.i
@@ -114,7 +114,7 @@ class HyperRAMPHY(Elaboratable):
         return m
 
     def ports(self):
-        return [self.clk, self.cs, self.dq_o, self.dq_i, self.dq_oe,
+        return [self.ck, self.cs, self.dq_o, self.dq_i, self.dq_oe,
                 self.rwds_o, self.rwds_oe]
 
 # HyperRAM --------------------------------------------------------------------
@@ -129,13 +129,15 @@ class HyperRAM(Peripheral, Elaboratable):
 
     This core favors portability and ease of use over performance.
     """
-    def __init__(self, *, io, phy_kls, latency=6):
+    def __init__(self, *, io, phy_kls, latency=6, bus=None,
+                                       features=frozenset()):
         super().__init__()
         self.io = io
         self.phy = phy_kls(io)
         self.latency = latency
         self.bus = wishbone.Interface(addr_width=21,
-                                      data_width=32, granularity=8)
+                                      data_width=32, granularity=8,
+                                      features=features)
         mmap = MemoryMap(addr_width=23, data_width=8)
         mmap.add_resource(object(), name="hyperram", size=2**23)
         self.bus.memory_map = mmap
@@ -148,7 +150,7 @@ class HyperRAM(Peripheral, Elaboratable):
         bus = self.bus
         comb, sync = m.d.comb, m.d.sync
 
-        clk       = self.phy.clk
+        ck       = self.phy.ck
         clk_phase = Signal(2)
         cs        = self.phy.cs
         ca        = Signal(48)
@@ -168,9 +170,9 @@ class HyperRAM(Peripheral, Elaboratable):
         sync += clk_phase.eq(clk_phase + 1)
         with m.Switch(clk_phase):
             with m.Case(1):
-                sync += clk.eq(cs)
+                sync += ck.eq(cs)
             with m.Case(3):
-                sync += clk.eq(0)
+                sync += ck.eq(0)
 
         # Data Shift Register (for write and read) ------------------------
         dqi = Signal(dw)
@@ -307,7 +309,7 @@ class HyperRAM(Peripheral, Elaboratable):
 if __name__ == '__main__':
     layout=[('rwds_o', 1), ('rwds_oe', 1),
             ('csn_o', 1), ('csn_oe', 1),
-            ('clk_o', 1), ('clk_oe', 1)]
+            ('ck_o', 1), ('ck_oe', 1)]
     for i in range(8):
         layout += [('d%d_o' % i, 1), ('d%d_oe' % i, 1), ('d%d_i' % i, 1)]
     io = Record(layout=layout)