sim: frv: fix up various missing prototype warnings

[binutils-gdb.git] / ld / ChangeLog

diff --git a/ld/ChangeLog b/ld/ChangeLog
index c84992d7633e3030122478f1f8f484066f622773..b4c49cc65139a38a9c3970ca6db8fe87fcc53f39 100644 (file)
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@@ -1,3 +1,33 @@
+2021-06-22  Nelson Chu  <nelson.chu@sifive.com>
+
+       * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.d: New testcase.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3a.s: Likewise.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.d: New testcase.
+       Should report error since the %pcrel_lo with addend refers to
+       %got_pcrel_hi.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3b.s: Likewise.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.d: New testcase.
+       Should report error since the %got_pcrel_hi with addend.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3c.s: Likewise.
+       * testsuite/ld-riscv-elf/pcrel-lo-addend-3.ld: Likewise.
+
+2021-06-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR ld/27998
+       * testsuite/ld-i386/i386.exp: Run PR ld/27998 tests.
+       * testsuite/ld-i386/pr27998a.d: New file.
+       * testsuite/ld-i386/pr27998a.s: Likewise.
+       * testsuite/ld-i386/pr27998b.d: Likewise.
+       * testsuite/ld-i386/pr27998b.s: Likewise.
+
+2021-06-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * testsuite/ld-x86-64/textrel-1.err: New file.
+       * testsuite/ld-x86-64/textrel-1a.s: Likewise.
+       * testsuite/ld-x86-64/textrel-1b.s: Likewise.
+       * testsuite/ld-x86-64/x86-64.exp: Run textrel-1 tests.
+
 2021-06-18  H.J. Lu  <hongjiu.lu@intel.com>
 
        * testsuite/ld-elf/property-and-1.d: Skip am33_2.0, hppa-hpux