Merge pull request #1175 from whitequark/write_verilog-fix-case-attr-position

[yosys.git] / libs / subcircuit / test_large.spl

diff --git a/libs/subcircuit/test_large.spl b/libs/subcircuit/test_large.spl
index 74a47d94f3221ea485696b84069a69d91a5e5641..e33e26985b56d10fe1beb856383661bb51d480dd 100644 (file)
--- a/libs/subcircuit/test_large.spl
+++ b/libs/subcircuit/test_large.spl
@@ -99,7 +99,7 @@ function makeGraph(seed, gates, primaryInputs, primaryOutputs)
 
        foreach netDecl (unusedOutpus)
                push primaryOutputs, netDecl;
-       
+
        return code;
 }