## Currently working on
- Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
+ - https://bugs.libre-soc.org/show_bug.cgi?id=575
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
+ - EUR
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
+ - EUR
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
- <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
- (total EUR 100 shared 50% with staf)
- EUR 50 lkcl
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 ioring and pads
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
- (total EUR 1500 shared 50% with LIP6)
- EUR 750 lkcl
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> multi-clock example
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
- (total EUR 400 shared 75% with LIP6)
- EUR 300 lkcl