## Currently working on
- Project Management
- - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=237> SV Encoding
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=664> SVP64 Branches
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
+ - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
+ - EUR 1250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
- <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
- <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
- <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
- <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
- - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
- <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
- <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
- https://bugs.libre-soc.org/show_bug.cgi?id=575
- EUR
- <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
- <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
- <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
- <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
- <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
- <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
- EUR 50, shared with samuel 10%
- <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+
- <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
- <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
- EUR 50, shared with samuel (EUR 350)
- <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
- <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
- <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
- - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
- <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
- EUR 200
- <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
- <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
## Completed but not yet submitted:
- - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
- - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+
+TO SORT
+
+28feb2022
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=485> icache
+ * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=469> dcache
+ * EUR 1500 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=491> mmu
+ * EUR 1000 (shared with [[tplaten]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL Formal (donated)
+ * EUR 500 (shared with [[programmerjake]])
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+ * EUR 400 (shared with [[programmerjake]])
+
+before that
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
+ - EUR 800
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+ - EUR 500
- <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
- <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- EUR 450
- Shared with Staf
- <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- - EUR 3000
- - shared with Staf 50%
- <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
- Project 2019-10-043 06dec2020 wishbone
- EUR (TBD)
## Submitted for NLNet RFP
-submitted but not confirmed paid:
+submitted 2021-dec-09 but not confirmed paid
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
+ - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
+ - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=200> IEEE754 FP layout
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+ - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+ - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
+
### Project 2019-02-012 04sep2020 Core
donation from NLNet confirmed received:
+### coriolis2 2021-apr-04
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+ - EUR 3000
+ - shared with Staf 50%
+
### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
- <https://bugs.libre-soc.org/show_bug.cgi?id=463>