(no commit message)

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 7bbf9a8afba1b8fccb542609140948d66d3b972b..1e644306f631e28cae79621ffbc6cc130d720407 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -12,12 +12,14 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcodes
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
    - EUR 
- - <https://bugs.libre-soc.org/show_bug.cgi?id=546> AV Opcode documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
    - EUR 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
@@ -64,6 +66,7 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
   - Project 2019-10-043 06dec2020 wishbone
   - EUR 0 (TBD)