pathname update

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index a00e1715a478c7fb9490c6095d92e946127a061f..26bfb72d87e1fd5df897fa118bf00635e1082fee 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -2,23 +2,58 @@
 
 Lead dev and Project Coordinator for Libre-SOC.
 
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
+* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+
 # Status tracking
 
 move things along from one stage to the next
 
 ## Currently working on
 
-* Project Management
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
-
+ - Project Management
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
  - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
     - functions needed for simulator
     - Shared 10% with [[mnolan]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
 
 ## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
 
 ## Submitted for NLNet RFP
 
@@ -26,6 +61,10 @@ submitted but not confirmed paid:
 
 ### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 
+## Paid
+
+donation from NLNet confirmed received:
+
 ### Project 2019-02-012 28-apr-2020
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
@@ -51,10 +90,6 @@ submitted but not confirmed paid:
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
 
-## Paid
-
-donation from NLNet confirmed received:
-
 ### Project 2019-02-012 Date 12mar2020
 
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250