* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
* <https://readthedocs.org/profiles/lkcl/> readthedocs link
+* <http://twitter.com/lkcl>
# Status tracking
## Currently working on
- Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=176> Partitioned Logic
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=167> Partitioned Mux
+ - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=709> better Partitioned eq (Assign)
+ - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=707> Partitioned Cat
+ - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=458> Partitioned Type 2 DSL
+ - EUR 1250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=549> Partitioned Logic docs
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=684> XLEN-16 fails
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=730> adapt ALU test cases
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
- <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
- <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
- <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
- https://bugs.libre-soc.org/show_bug.cgi?id=575
- EUR
- <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
- <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
- - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
- - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450> Create HDL MMU
- <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
- <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
- <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
- <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
- <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
- <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
- - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
- <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
- EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
- - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
- <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API
- <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
- donated
- <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation
## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=686> create Power ISA test API
+ - EUR 1600
+ - EUR 800 shared with [[klehman]]
+ - EUR 800 shared with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=712> ISACaller supporting XLEN
+ - EUR 500 shared between:
+ - EUR 100 [[lkcl]]
+ - EUR 325 dmitry
+ - EUR 75 maciej
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=703> SVP64 preliminary decode
+ - EUR 800
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425> div errors
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432> mul overflow incorrect
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
+ - EUR 800 shared between:
+ - EUR 500 [[lkcl]]
+ - EUR 300 [[tplaten]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - EUR 5500 shared between:
+ - EUR 3850 lkcl
+ - EUR 1650 Others
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+ - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+ - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+ - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
+
- <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
- EUR 150
submitted but not confirmed paid:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+
### Project 2019-02-012 04sep2020 Core
- <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex