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add CIX mode in LDST field
[libreriscv.git] / lkcl.mdwn
diff --git a/lkcl.mdwn b/lkcl.mdwn
index f7fcde7b8dcb0379b55aaf6b6e30ec3494664283..a030d474104caaeccfa28dacc664ceb822772563 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -2,31 +2,99 @@
 
 Lead dev and Project Coordinator for Libre-SOC.
 
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
+* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+
 # Status tracking
 
 move things along from one stage to the next
 
 ## Currently working on
 
-* Project Management
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=132> simd partitioned signal
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
+ - Project Management
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+    - functions needed for simulator
+    - Shared 10% with [[mnolan]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=323> CR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
 
 ## Completed but not yet submitted:
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
 
 ## Submitted for NLNet RFP
 
 submitted but not confirmed paid:
 
-### Project 2019-02-012 Date 28jan2020
-
-* admin tasks
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
+### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 
 ## Paid
 
 donation from NLNet confirmed received:
 
+### Project 2019-02-012 28-apr-2020
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
+   - 6600 scoreboard multi-read/write
+   - EUR 600
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
+   - Partitioned equals and greater than comparison
+   - Shared 50% with [[mnolan]] 
+   - EUR 200 (each)
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
+   - partitioned scalar/vector shift
+   - Shared 50% with [[lkcl]]
+   - EUR 350 (each)
+
+### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER 
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
+    - auto-parser of POWER9
+    - Shared 50% with [[mnolan]]
+    - EUR 500 (each)
+
+### Project 2019-10-029 Date 14mar2020
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
+
+### Project 2019-02-012 Date 12mar2020
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
+
+### Project 2019-02-012 Date 28jan2020
+
+* admin tasks
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
+
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