(no commit message)

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 783779fabcdfd4d1c9db6b3748455b00d2decadd..a35752b81e01aba2dd6605d76558c62514b2da59 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -12,6 +12,14 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
+ - https://bugs.libre-soc.org/show_bug.cgi?id=575
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
+   - EUR 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
@@ -55,19 +63,56 @@ move things along from one stage to the next
 
 ## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+   - EUR 200
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+   - EUR 200
+   - donated
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
+   - EUR 700
+   - (lip6.fr donated)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
+   - (total EUR 400 25% donated by LIP6)
+   - EUR 100 lkcl
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
+   - EUR 900
+   - shared with [[lxo]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
+   - EUR 1100
+   - shared with lauri, jacob
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
+   - EUR 1250
+   - Shared 50% with Staf
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
+   - EUR 300
+   - Shared with Staf, cole
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
+   - EUR 450
+   - Shared with Staf
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+   - EUR 3000
+   - shared with Staf 50%
  - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
-  - Project 2019-10-043 06dec2020 wishbone
-  - EUR 0 (TBD)
+   - Project 2019-10-043 06dec2020 wishbone
+   - EUR (TBD)
 
 ### Project 2019-10-029 14mar2020 coriolis2
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
    - (total EUR 100 shared 50% with staf)
    - EUR 50 lkcl
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 ioring and pads
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=507> ls180 ioring and pads
    - (total EUR 1500 shared 50% with LIP6)
    - EUR 750 lkcl
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> multi-clock example
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
    - (total EUR 400 shared 75% with LIP6)
    - EUR 300 lkcl