docs/firststeps: instruction execution

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 56e92476285f7eeb544a3d5c4c71ff82c27b1c97..b169af0f6cfc408c14f912da4ef263b50db3e94d 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,6 +4,7 @@ Lead dev and Project Coordinator for Libre-SOC.
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* <https://readthedocs.org/profiles/lkcl/> readthedocs link
 
 # Status tracking
 
@@ -12,16 +13,18 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  - https://bugs.libre-soc.org/show_bug.cgi?id=575
  - <https://bugs.libre-soc.org/show_bug.cgi?id=53> 3D Custom instructions
  - <https://bugs.libre-soc.org/show_bug.cgi?id=565> Partitioning Proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documrntation
-   - EUR 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=546> Data merging FSM
    - EUR 
- - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
@@ -63,12 +66,43 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
   - donated
   - parent #195
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
 
-- <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+   - EUR 200
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+   - EUR 200
+   - donated
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
+   - EUR 700
+   - (lip6.fr donated)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
+   - (total EUR 400 25% donated by LIP6)
+   - EUR 100 lkcl
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=556> SV Overview
+   - EUR 900
+   - shared with [[lxo]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=557> AV Opcode documentation
+   - EUR 1100
+   - shared with lauri, jacob
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=620> Cocotb simulation
    - EUR 1250
-   - Shated 50% with Staf
+   - Shared 50% with Staf
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=502> 4k SRAM
+   - EUR 300
+   - Shared with Staf, cole
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=506> IORing
+   - EUR 450
+   - Shared with Staf
  - <https://bugs.libre-soc.org/show_bug.cgi?id=606> PowerDecoder2 simplification
  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
    - EUR 3000