## Currently working on
- Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
- <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
- <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
- - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder with [[mnolan]]
- - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
- - functions needed for simulator
- - Shared 10% with [[mnolan]]
- <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
- - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
- - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=315> SPR pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+ - shared with cole
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
+ - EUR 50, shared with samuel 10%
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
- <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
- - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
- - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
- - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
+ - EUR 50, shared with samuel (EUR 350)
- <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
- <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
- - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
- - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
- - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
- - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
- <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
- - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
+ - EUR 400 shared 25% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
+ - EUR 500 shared [[mnolan]] samuel, TBD split
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST cache-inhibit
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=493> DMI to JTAG
+ - EUR 250 (share with cole)
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=508> pin-package for 180nm ASIC
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+- <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
+ - EUR 250 lkcl, EUR 50 [[programmerjake]], total EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=482> LD/ST sign-extend
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=478> mfcr FXM
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
+ - EUR 450
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=519> ULX3S boot
+
+donated:
+
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> POWER Decoder
+ - with [[lkcl]]
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=208> CORDIC
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+ - functions needed for simulator
+ - Shared 90% with [[lkcl]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=211> parent #198
+ - Formal proof of decoder
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> parent #195
+ - POWER9 ALU proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> parent #195
+ - POWER9 CR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> parent #195
+ - POWER9 BRANCH proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> parent #195
+ - POWER9 LOGICAL proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> parent #195
+ - POWER9 ROTATE proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=342> parent #197
+ - MultiCompUnit (and Function Units) proof
## Submitted for NLNet RFP
submitted but not confirmed paid:
+### Project 2019-02-012 04sep2020 Core
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
+ - EUR 2000 total, shared with florent. EUR 1200
+
### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
## Paid
donation from NLNet confirmed received:
+### 2019-10P-046 19-aug-2020 NLNet 2019-10-046 Formal Standards OpenPOWER
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
+ - EUR 2000, python POWER9 simulator
+ - Shared 50% with [[mnolan]], EUR 1000
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+ - EUR 250, functions needed for simulator
+ - Shared 20% with [[mnolan]], EUR 50
+
+#### proofs 2019-10-032
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
+ - EUR 500 shared 20% samuel, EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
+ - EUR 300 shared 1/6 [[mnolan]] EUR 50
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
+ - EUR 400 shared 25% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
+ - EUR 150
+
+### wishbone 2019-10-043
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
+ - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
+ - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
+ - EUR 250
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
+ - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
+ - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
+ - EUR 400, 50% shared [[programmerjake]] EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
+ - EUR 750, 33% shared [[programmerjake]] EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
+ - EUR 200 50% shared, cole, EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
+ - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
+ - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
+ - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+ - EUR 400 shared 50% [[mnolan]] EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+ - EUR 250 shared 40% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+ - EUR 300 shared 1/3 [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+ - EUR 300 shared 50% [[mnolan]] EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
+ - EUR 750
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
+ - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
+ - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
+
### Project 2019-02-012 28-apr-2020
- <https://bugs.libre-soc.org/show_bug.cgi?id=292>