(no commit message)

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index a09c67397289b2cc62980a67e57ae2d35c39824f..d45be1a157e9f4143c30bfa41b04fa79c094dc93 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -4,6 +4,8 @@ Lead dev and Project Coordinator for Libre-SOC.
 
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
+* <https://readthedocs.org/profiles/lkcl/> readthedocs link
+* <http://twitter.com/lkcl>
 
 # Status tracking
 
@@ -12,6 +14,13 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  - https://bugs.libre-soc.org/show_bug.cgi?id=575
@@ -21,9 +30,7 @@ move things along from one stage to the next
    - EUR 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=213> SV Spec
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
- - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
@@ -46,10 +53,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
- - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
    - donated
@@ -60,9 +63,38 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=340> POWER9 ROTATE proof
   - donated
   - parent #195
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+   - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+   - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+   - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
+
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+   - EUR 200
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+   - EUR 150
+   - donated
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+   - EUR 200
+   - donated
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 tutorial
+   - EUR 700
+   - (lip6.fr donated)
  - <https://bugs.libre-soc.org/show_bug.cgi?id=521> multi-clock example
    - (total EUR 400 25% donated by LIP6)
    - EUR 100 lkcl
@@ -152,6 +184,8 @@ move things along from one stage to the next
 
 submitted but not confirmed paid:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
+
 ### Project 2019-02-012 04sep2020 Core
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex