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[libreriscv.git] / lkcl.mdwn
diff --git a/lkcl.mdwn b/lkcl.mdwn
index 7870f1e3463526de31b9680f40e250499a50b098..db0229b595cd4305dc3cf2143f2e87a06c1bac5c 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -1,6 +1,9 @@
 # Luke Kenneth Casson Leighton
 
-Lead dev and Project Coordinator for LibreSOC.
+Lead dev and Project Coordinator for Libre-SOC.
+
+* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
+* [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
 
 # Status tracking
 
@@ -8,23 +11,149 @@ move things along from one stage to the next
 
 ## Currently working on
 
-* Project Management
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=132> simd partitioned signal
+ - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=416> DEC/TB
+   - EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=468> wishbone downconverter
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=81> 6600 scoreboard
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=206> branch prediction research
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=216> LDST buffer
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=448> MUL tests
+   - shared with cole
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=340> SHIFTROT proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=348> SPR pipe
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=418> SPR proof
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=350> LDST RA=0 test
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=361> RA=0 tests
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=407> XICS
+   - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=412> litex
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=415> misc opcodes
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=349> privileged detection
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=310> FU multiple tasks
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=335> Branch proof
+   - EUR 400 shared 25% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=306> ALU proof
+   - EUR 500 shared [[mnolan]] samuel, TBD split
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial
+## Completed but not yet submitted:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=476> addme bug
 
-## Completed
+## Submitted for NLNet RFP
 
-completed but not yet submitted:
+submitted but not confirmed paid:
 
-* <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range
+### 2019-10P-046 19-aug-2020  NLNet 2019-10-046 Formal Standards OpenPOWER 
 
-## Submitted for NLNet RFP
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=463>
+    - EUR 2000, python POWER9 simulator
+    - Shared 50% with [[mnolan]], EUR 1000
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=272>
+    - EUR 250, functions needed for simulator
+    - Shared 20% with [[mnolan]], EUR 50
 
-submitted but not confirmed paid:
+#### proofs 2019-10-032
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=421> Trap proof
+   - EUR 500 shared 20% samuel, EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=332> CR proof
+   - EUR 300 shared 1/6 [[mnolan]] EUR 50
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=331> Logic proof
+   - EUR 400 shared 25% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=312> countzero proof
+   - EUR 150
+
+### wishbone 2019-10-043
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=460> Document 6600
+   - EUR 500
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=393> WB to LDST
+    - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=414> DMI interface
+    - EUR 250
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=186> opcode decoder
+   - EUR 500, shared 40%, with [[mnolan]] (40%), [[programmerjake]] (20%), EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=339> SHIFTROT pipe
+   - EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=441> test improvement
+   - EUR 400, 50% shared [[programmerjake]] EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
+   - EUR 750, 33% shared [[programmerjake]] EUR 250
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=351> virtual regfile port
+   - EUR 200 50% shared, cole, EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
+   - EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=325> Trap pipe
+   - EUR 500 60% shared, cole (20%) samuel (20%), EUR 300
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=382> SRAM wishbone object
+   - EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=305> ALU pipe
+   - EUR 400 shared 50% [[mnolan]] EUR 200
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=313> Branch pipe
+   - EUR 250 shared 40% [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=314> CR pipe
+   - EUR 300 shared 1/3 [[mnolan]] EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
+   - EUR 300 shared 50% [[mnolan]] EUR 150
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=346> regfile-core
+   - EUR 750
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
+  - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
+  - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
+   - EUR 100
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
+   - EUR 1500 shared with [[programmerjake]] 1/3 (EUR 500)
+ 
+
+### Project 2019-02-012 Date {TEMPLATE INSERT DATE}
 
 ## Paid
 
 donation from NLNet confirmed received:
 
+### Project 2019-02-012 28-apr-2020
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=292>
+   - 6600 scoreboard multi-read/write
+   - EUR 600
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=171> parent #48
+   - Partitioned equals and greater than comparison
+   - Shared 50% with [[mnolan]] 
+   - EUR 200 (each)
+ - <http://bugs.libre-riscv.org/show_bug.cgi?id=173> parent #48
+   - partitioned scalar/vector shift
+   - Shared 50% with [[lkcl]]
+   - EUR 350 (each)
+
+### 2019-10P-046 28-apr-2020  NLNet 2019 Formal Standards OpenPOWER 
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=269> parent #241
+    - auto-parser of POWER9
+    - Shared 50% with [[mnolan]]
+    - EUR 500 (each)
+
+### Project 2019-10-029 Date 14mar2020
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=178> coriolis2 start/tutorial EUR 1200
+
+### Project 2019-02-012 Date 12mar2020
+
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=113> fcvt range 100% EUR 250
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=171> 50% with [[mnolan]] EUR 200
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=173> dynamic shift 50% with [[mnolan]] EUR 350
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=127> EUR 900 shared with [[programmerjake]]
+
+### Project 2019-02-012 Date 28jan2020
+
+* admin tasks
+* <http://bugs.libre-riscv.org/show_bug.cgi?id=147>
+
http://libre-riscv.org ikiwiki