(no commit message)

[libreriscv.git] / lkcl.mdwn

diff --git a/lkcl.mdwn b/lkcl.mdwn
index b65e60322fc0c7f66d82e7b400b55100f32f0902..db44c06ceb0c2d6d610b1fb41d93ac88b5ee2b94 100644 (file)
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -5,6 +5,7 @@ Lead dev and Project Coordinator for Libre-SOC.
 * [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=lkcl&emailassigned_to1=1&emailtype1=substring&resolution=---)
 * [180nm task list](https://bugs.libre-soc.org/showdependencytree.cgi?maxdepth=1&id=383&hide_resolved=1)
 * <https://readthedocs.org/profiles/lkcl/> readthedocs link
+* <http://twitter.com/lkcl>
 
 # Status tracking
 
@@ -13,8 +14,13 @@ move things along from one stage to the next
 ## Currently working on
 
  - Project Management
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=654> symbiflow shared with [[veera]]
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=701> DCT FFT documentation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=658> SVSTATE extended to 64 bit
  - <https://bugs.libre-soc.org/show_bug.cgi?id=241> OpenPOWER simulator
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=647> ISACaller basic FP
  - <https://bugs.libre-soc.org/show_bug.cgi?id=52> SVP64 simulation
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=604> ISACaller RADIX MMU
  - <https://bugs.libre-soc.org/show_bug.cgi?id=609> SVSTATE DMI
  - <https://bugs.libre-soc.org/show_bug.cgi?id=588> SVP64 PowerDecoder2
  - https://bugs.libre-soc.org/show_bug.cgi?id=575
@@ -26,7 +32,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=214> ISAMux writeup
  - <https://bugs.libre-soc.org/show_bug.cgi?id=202> HDL changes for coriolis2
  - <https://bugs.libre-soc.org/show_bug.cgi?id=425>
- - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
  - <https://bugs.libre-soc.org/show_bug.cgi?id=432>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=450>
  - <https://bugs.libre-soc.org/show_bug.cgi?id=458> PartitionedSignal Module
@@ -49,10 +54,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=482> mul bug
  - <https://bugs.libre-soc.org/show_bug.cgi?id=427> LD/ST cache-inhibit
    - EUR 200
- - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
- - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
- - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
- - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=64> data handling API 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=211> Formal proof of decoder
    - donated
@@ -66,6 +67,19 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=639> SVP64 test documentation 
 
 ## Completed but not yet submitted:
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=699> SVP64 Draft 0.1
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=653> DCT and FFT REMAP
+   - EUR 1600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=702> Matrix REMAP tests
+   - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=578> SVP64 generator
+   - EUR 600
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=466> 3D MESA planning
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=490> litex peripheral set
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=514> ls180 reset review
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=515> JTAG boot upload/init
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=511> JTAG IO Boundary test
+
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=330> Logic pipe
    - EUR 150