Merge pull request #2135 from boqwxp/qbfsat-timeinfo

[yosys.git] / manual / APPNOTE_010_Verilog_to_BLIF.tex

diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex
index 3e36fa386b59bc7af27a07863e2601060c1e912b..0ecdf61942245810f0663fc674da99ad96e44713 100644 (file)
--- a/manual/APPNOTE_010_Verilog_to_BLIF.tex
+++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex
@@ -100,7 +100,7 @@ regression testing Yosys.
 
 \section{Getting Started}
 
-We start our tour with the Navré processor from yosys-bigsim. The Navré
+We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e
 processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt
 softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is
 using only features that map nicely to the BLIF format, for example it only
@@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that.
 \medskip
 
 So now we have the final synthesis script for generating a BLIF file
-for the Navré CPU:
+for the Navr\'e CPU:
 
 \begin{figure}[H]
 \begin{lstlisting}[language=sh]
@@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing
 \url{https://github.com/cliffordwolf/yosys-bigsim}
 
 \bibitem{navre}
-Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
+Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\
 \url{http://opencores.org/project,navre}
 
 \bibitem{amber}