Fix muxcover and its techmapping

[yosys.git] / manual / APPNOTE_010_Verilog_to_BLIF.tex

diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex
index bba17c9027b2ad6865c3cbd9f7cd4dacb2fba47b..0ecdf61942245810f0663fc674da99ad96e44713 100644 (file)
--- a/manual/APPNOTE_010_Verilog_to_BLIF.tex
+++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex
@@ -61,7 +61,7 @@ to easily create complex designs from small HDL code. It is the preferred
 method of design entry for many designers\footnote{The other half prefers VHDL,
 a very different but -- of course -- equally powerful language.}.
 
-The Berkeley Logic Interchange Format (BLIF) is a simple file format for
+The Berkeley Logic Interchange Format (BLIF) \cite{blif} is a simple file format for
 exchanging sequential logic between programs. It is easy to generate and
 easy to parse and is therefore the preferred method of design entry for
 many authors of logic synthesis tools.
@@ -100,7 +100,7 @@ regression testing Yosys.
 
 \section{Getting Started}
 
-We start our tour with the Navré processor from yosys-bigsim. The Navré
+We start our tour with the Navr\'e processor from yosys-bigsim. The Navr\'e
 processor \cite{navre} is an Open Source AVR clone. It is a single module ({\tt
 softusb\_navre}) in a single design file ({\tt softusb\_navre.v}). It also is
 using only features that map nicely to the BLIF format, for example it only
@@ -150,11 +150,11 @@ write_blif softusb_navre.blif
 \end{figure}
 
 The first and last line obviously read the Verilog file and write the BLIF
-file. 
+file.
 
 \medskip
 
-The 2nd line checks the design hierarchy and instantiates parametrized 
+The 2nd line checks the design hierarchy and instantiates parametrized
 versions of the modules in the design, if necessary. In the case of this
 simple design this is a no-op. However, as a general rule a synthesis script
 should always contain this command as first command after reading the input
@@ -174,7 +174,7 @@ instead of {\tt opt}.
 \item The command {\tt proc} converts {\it processes} (Yosys' internal
 representation of Verilog {\tt always}- and {\tt initial}-blocks) to circuits
 of multiplexers and storage elements (various types of flip-flops).
-\item The command {\tt memory} converts Yosys' internal representations of 
+\item The command {\tt memory} converts Yosys' internal representations of
 arrays and array accesses to multi-port block memories, and then maps this
 block memories to address decoders and flip-flops, unless the option {\tt -nomap}
 is used, in which case the multi-port block memories stay in the design
@@ -226,7 +226,7 @@ further processed using custom commands. But in this case we don't want that.
 \medskip
 
 So now we have the final synthesis script for generating a BLIF file
-for the Navré CPU:
+for the Navr\'e CPU:
 
 \begin{figure}[H]
 \begin{lstlisting}[language=sh]
@@ -358,7 +358,7 @@ process this cell.
 #define BITMAP_SIZE 64
 #define OUTPORT 0x10000000
 
-static uint16_t bitmap[BITMAP_SIZE/32];
+static uint32_t bitmap[BITMAP_SIZE/32];
 
 static void bitmap_set(uint32_t idx) { bitmap[idx/32] |= 1 << (idx % 32); }
 static bool bitmap_get(uint32_t idx) { return (bitmap[idx/32] & (1 << (idx % 32))) != 0; }
@@ -403,7 +403,7 @@ file into ABC's internal format as well.
 
 The only thing left to write about the simulation itself is that it probably
 was one of the most energy inefficient and time consuming ways of successfully
-calculating the first 50 primes the author has ever conducted.
+calculating the first 31 primes the author has ever conducted.
 
 \section{Limitations}
 
@@ -445,7 +445,7 @@ yosys-bigsim, a collection of real-world Verilog designs for regression testing
 \url{https://github.com/cliffordwolf/yosys-bigsim}
 
 \bibitem{navre}
-Sebastien Bourdeauducq. Navré AVR clone (8-bit RISC). \\
+Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\
 \url{http://opencores.org/project,navre}
 
 \bibitem{amber}
@@ -456,6 +456,10 @@ Conor Santifort. Amber ARM-compatible core. \\
 Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. \\
 \url{http://www.eecs.berkeley.edu/~alanmi/abc/}
 
+\bibitem{blif}
+Berkeley Logic Interchange Format (BLIF) \\
+\url{http://vlsi.colorado.edu/~vis/blif.ps}
+
 \end{thebibliography}