kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / APPNOTE_012_Verilog_to_BTOR.tex

diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex
index 67f15bc264dd840aff9124bda31e182c716e82a7..1bc2778760e46c70333382930b772061c3f52fa0 100644 (file)
--- a/manual/APPNOTE_012_Verilog_to_BTOR.tex
+++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex
@@ -89,7 +89,7 @@ This Application Note is based on GIT Rev. {\tt 082550f} from
 We assume that the Verilog design is synthesizable and we also assume
 that the design does not have multi-dimensional memories.  As BTOR
 implicitly initializes registers to zero value and memories stay
-uninitilized, we assume that the Verilog design does
+uninitialized, we assume that the Verilog design does
 not contain initial blocks. For more details about the BTOR format,
 please refer to~\cite{btor}.
 
@@ -208,7 +208,7 @@ read_verilog -sv $1;
 hierarchy -top $3; hierarchy -libdir $DIR;
 hierarchy -check;
 proc; opt;
-opt_const -mux_undef; opt;
+opt_expr -mux_undef; opt;
 rename -hide;;;
 splice; opt;
 memory_dff -wr_only; memory_collect;;
@@ -263,7 +263,7 @@ read_verilog -sv $1;
 hierarchy -top $3; hierarchy -libdir $DIR;
 hierarchy -check;
 proc; opt;
-opt_const -mux_undef; opt;
+opt_expr -mux_undef; opt;
 rename -hide;;;
 splice; opt;
 memory;;