Improve igloo2 example

[yosys.git] / manual / CHAPTER_Appnotes.tex

diff --git a/manual/CHAPTER_Appnotes.tex b/manual/CHAPTER_Appnotes.tex
index 6f03b79cfc82c0af50df15473dbde1152d1ce670..e0d093290e400622decdfc06e4925a7f453d5154 100644 (file)
--- a/manual/CHAPTER_Appnotes.tex
+++ b/manual/CHAPTER_Appnotes.tex
@@ -7,7 +7,7 @@
 % \end{fixme}
 %
 % \section{Synthesizing using a Cell Library in Liberty Format}
-% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
+% \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist}
 % \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
 
 This appendix contains copies of the Yosys application notes.
@@ -15,6 +15,7 @@ This appendix contains copies of the Yosys application notes.
 \begin{itemize}
 \item Yosys AppNote 010: Converting Verilog to BLIF \dotfill Page \pageref{app:010} \hskip2cm\null
 \item Yosys AppNote 011: Interactive Design Investigation \dotfill Page \pageref{app:011} \hskip2cm\null
+\item Yosys AppNote 012: Converting Verilog to BTOR \dotfill Page \pageref{app:012} \hskip2cm\null
 \end{itemize}
 
 \eject\label{app:010}
@@ -23,3 +24,6 @@ This appendix contains copies of the Yosys application notes.
 \eject\label{app:011}
 \includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_011_Design_Investigation.pdf}
 
+\eject\label{app:012}
+\includepdf[pages=-,pagecommand=\thispagestyle{plain}]{APPNOTE_012_Verilog_to_BTOR.pdf}
+