kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / CHAPTER_Approach.tex

diff --git a/manual/CHAPTER_Approach.tex b/manual/CHAPTER_Approach.tex
index 691225805996fd72b6420a2f2609f1213ba2ffa0..4b170ee0ae8f1d0d631121d9dd90ecdebaffaedf 100644 (file)
--- a/manual/CHAPTER_Approach.tex
+++ b/manual/CHAPTER_Approach.tex
@@ -59,7 +59,7 @@ script.
 
 \section{Internal Formats in Yosys}
 
-Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a verilog
+Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a Verilog
 input file. This format is simply called {\it AST} and is generated by the Verilog Frontend. This data structure
 is consumed by a subsystem called {\it AST Frontend}\footnote{In Yosys the term {\it pass} is only used to
 refer to commands that operate on the RTLIL data structure.}. This AST Frontend then generates a design in Yosys'
@@ -107,7 +107,7 @@ from the input file {\tt design.v} to a gate-level netlist {\tt synth.v} using t
 described by the Liberty file \citeweblink{LibertyFormat} {\tt cells.lib}:
 
 \begin{lstlisting}[language=sh,numbers=left,frame=single]
-# read input file tpo internal representation
+# read input file to internal representation
 read_verilog design.v
 
 # convert high-level behavioral parts ("processes") to d-type flip-flops and muxes