Added $assert cell

[yosys.git] / manual / CHAPTER_CellLib.tex

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index b84e1b30e26c45f34624849029e074cf8d3ddb13..b848a2b60a46cc0539cff3ea7cb6683c31ae77d8 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -418,3 +418,7 @@ from the gate level logic network can be mapped to physical flip-flop cells from
 pass. The combinatorial logic cells can be mapped to physical cells from a Liberty file via ABC \citeweblink{ABC}
 using the {\tt abc} pass.
 
+\begin{fixme}
+Add information about {\tt \$assert} cells.
+\end{fixme}
+