and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
synthesis tool would have been needed as basis to build upon. The main advantages
of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
-to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
+to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
such a tool would have to provide a feature-complete implementation of the
synthesizable HDL subset.
Yosys.
Chapter~\ref{chapter:overview} contains a more detailed overview of the
-implementation of Yosys. This chapter covers the data structures used in
+implementation of Yosys. This chapter covers the data structures used in
Yosys to represent a design in detail and is therefore recommended reading
for everyone who is interested in understanding the Yosys internals.
Yosys source code. The chapter concludes with an example loadable module
for Yosys.
-Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
+Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
cover three important pieces of the synthesis pipeline: The Verilog frontend,
the optimization passes and the technology mapping to the target architecture,
respectively.