Merge pull request #1241 from YosysHQ/clifford/jsonfix

[yosys.git] / manual / CHAPTER_Optimize.tex

diff --git a/manual/CHAPTER_Optimize.tex b/manual/CHAPTER_Optimize.tex
index 07f5a26e6f7853e30e2ab09f18f8750abba4a126..eee92ef5c5a3fbcf471f14c88e0773533c666521 100644 (file)
--- a/manual/CHAPTER_Optimize.tex
+++ b/manual/CHAPTER_Optimize.tex
@@ -16,13 +16,13 @@ passes that each perform a simple optimization:
 \item Once at the beginning of {\tt opt}:
 \begin{itemize}
 \item {\tt opt\_expr}
-\item {\tt opt\_share -nomux}
+\item {\tt opt\_merge -nomux}
 \end{itemize}
 \item Repeat until result is stable:
 \begin{itemize}
 \item {\tt opt\_muxtree}
 \item {\tt opt\_reduce}
-\item {\tt opt\_share}
+\item {\tt opt\_merge}
 \item {\tt opt\_rmdff}
 \item {\tt opt\_clean}
 \item {\tt opt\_expr}
@@ -130,7 +130,7 @@ This pass identifies unused signals and cells and removes them from the design.
 creates an \B{unused\_bits} attribute on wires with unused bits. This attribute can be
 used for debugging or by other optimization passes.
 
-\subsection{The opt\_share pass}
+\subsection{The opt\_merge pass}
 
 This pass performs trivial resource sharing. This means that this pass identifies cells
 with identical inputs and replaces them with a single instance of the cell.
@@ -222,6 +222,10 @@ This heuristic has proven to work very well. It is possible to overwrite it by s
 and setting \B{fsm\_encoding}{\tt = "none"} on registers that match the above criteria
 but should not be considered FSM state registers.
 
+Note however that marking state registers with \B{fsm\_encoding} that are not
+suitable for FSM recoding can cause synthesis to fail or produce invalid
+results.
+
 \subsection{FSM Extraction}
 
 The {\tt fsm\_extract} pass operates on all state signals marked with the