kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / CHAPTER_Overview.tex

diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 1a25c477ff21bdeea2228d584af3e923a059b602..be37d8d39c5490a694db8d6a8c19b26978d6f1f3 100644 (file)
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -234,6 +234,8 @@ An RTLIL::Wire object has the following properties:
 \item The wire name
 \item A list of attributes
 \item A width (buses are just wires with a width > 1)
+\item Bus direction (MSB to LSB or vice versa)
+\item Lowest valid bit index (LSB or MSB depending on bus direction)
 \item If the wire is a port: port number and direction (input/output/inout)
 \end{itemize}
 
@@ -246,6 +248,11 @@ This makes some aspects of RTLIL more complex but enables Yosys to be used for
 coarse grain synthesis where the cells of the target architecture operate on
 entire signal vectors instead of single bit wires.
 
+In Verilog and VHDL, busses may have arbitrary bounds, and LSB can have either
+the lowest or the highest bit index. In RTLIL, bit 0 always corresponds to LSB;
+however, information from the HDL frontend is preserved so that the bus will be
+correctly indexed in error messages, backend output, constraint files, etc.
+
 An RTLIL::Cell object has the following properties:
 
 \begin{itemize}
@@ -331,8 +338,9 @@ to update {\tt \textbackslash{}q}.
 An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and
 exactly one RTLIL::CaseRule object, which is called the {\it root case}.
 
-An RTLIL::SyncRule object contains an (optional) synchronization condition
-(signal and edge-type) and zero or more assignments (RTLIL::SigSig).
+An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or
+more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial
+loops when a latch should be inferred instead.
 
 An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig)
 and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a