Merge pull request #1997 from whitequark/document-ootb

[yosys.git] / manual / CHAPTER_Prog.tex

diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex
index b6157aa1c9d676e9dccee2518c343e0e4e438e78..3cbc95a195de0783cf023c1558b48b7ec3a1a967 100644 (file)
--- a/manual/CHAPTER_Prog.tex
+++ b/manual/CHAPTER_Prog.tex
@@ -2,20 +2,25 @@
 \chapter{Programming Yosys Extensions}
 \label{chapter:prog}
 
-\begin{fixme}
-This chapter will contain a guided tour to the Yosys APIs and conclude
-with an example module.
-\end{fixme}
+This chapter contains some bits and pieces of information about programming
+yosys extensions. Also consult the section on programming in the ``Yosys
+Presentation'' (can be downloaded from the Yosys website as PDF) and don't
+be afraid to ask questions on the Yosys Subreddit.
 
-\section{Programming with RTLIL}
-\section{Internal Utility Libraries}
-\section{Loadable Modules}
+\section{The ``CodingReadme'' File}
 
-\section{Example Module}
+The following is an excerpt of the {\tt CodingReadme} file from the Yosys source tree.
 
-\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc}
+\lstinputlisting[title=CodingReadme,rangeprefix=--,rangesuffix=--,includerangemarker=false,linerange=snip-snap,numbers=left,frame=single]{../CodingReadme}
 
-\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile}
+\section{The ``stubsnets'' Example Module}
 
-\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v}
+The following is the complete code of the ``stubsnets'' example module. It is included in the Yosys source distribution as {\tt manual/CHAPTER\_Prog/stubnets.cc}.
+
+
+\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{CHAPTER_Prog/stubnets.cc}
+
+\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{CHAPTER_Prog/Makefile}
+
+\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{CHAPTER_Prog/test.v}