kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero

[yosys.git] / manual / CHAPTER_StateOfTheArt.tex

diff --git a/manual/CHAPTER_StateOfTheArt.tex b/manual/CHAPTER_StateOfTheArt.tex
index d6a5c9b187c20aa1e60fe73064a03536f5e1bd58..2d0c77a01a5f8e6dbb3cb06f4d1b10c3c4815a35 100644 (file)
--- a/manual/CHAPTER_StateOfTheArt.tex
+++ b/manual/CHAPTER_StateOfTheArt.tex
@@ -55,18 +55,18 @@ with a summary of the results.
 
 \begin{figure}[t!]
        \begin{minipage}{7.7cm}
-               \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always01_pub.v}
+               \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always01_pub.v}
        \end{minipage}
        \hfill
        \begin{minipage}{7.7cm}
-               \lstinputlisting[frame=single,language=Verilog]{FILES_StateOfTheArt/always02_pub.v}
+               \lstinputlisting[frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always02_pub.v}
        \end{minipage}
        \caption{1st and 2nd Verilog always examples}
        \label{fig:StateOfTheArt_always12}
 \end{figure}
 
 \begin{figure}[!]
-       \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always03.v}
+       \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always03.v}
        \caption{3rd Verilog always example}
        \label{fig:StateOfTheArt_always3}
 \end{figure}
@@ -107,7 +107,7 @@ The first example is only using the most fundamental Verilog features. All
 tools under test were able to successfully synthesize this design.
 
 \begin{figure}[b!]
-       \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/arrays01.v}
+       \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/arrays01.v}
        \caption{Verilog array example}
        \label{fig:StateOfTheArt_arrays}
 \end{figure}
@@ -155,7 +155,7 @@ For this design HANA, vl2m and ODIN-II generate error messages indicating that
 arrays are not supported.
 
 \begin{figure}[t!]
-       \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen01.v}
+       \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen01.v}
        \caption{Verilog for loop example}
        \label{fig:StateOfTheArt_for}
 \end{figure}
@@ -171,7 +171,7 @@ by continuing tests on this aspect of Verilog synthesis such as synthesis of dua
 memories, correct handling of write collisions, and so forth.
 
 \begin{figure}[t!]
-       \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen02.v}
+       \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen02.v}
        \caption{Verilog generate example}
        \label{fig:StateOfTheArt_gen}
 \end{figure}
@@ -248,7 +248,7 @@ passes). This architecture will simplify implementing additional HDL front
 ends and/or additional synthesis passes.
 
 Chapter~\ref{chapter:eval} contains a more detailed evaluation of Yosys using real-world
-designes that are far out of reach for any of the other tools discussed in this appendix.
+designs that are far out of reach for any of the other tools discussed in this appendix.
 
 \vskip2cm
 \begin{table}[h]