\begin{sloppypar}
The Verilog Lexer is written using the lexer generator {\it flex} \citeweblink{flex}. Its source code
-can be found in {\tt frontends/verilog/lexer.l} in the Yosys source tree.
+can be found in {\tt frontends/verilog/verilog\_lexer.l} in the Yosys source tree.
The lexer does little more than identifying all keywords and literals
recognised by the Yosys Verilog frontend.
\end{sloppypar}
-The lexer keeps track of the current location in the verilog source code using
+The lexer keeps track of the current location in the Verilog source code using
some global variables. These variables are used by the constructor of AST nodes
to annotate each node with the source code location it originated from.
\subsection{The Verilog Parser}
The Verilog Parser is written using the parser generator {\it bison} \citeweblink{bison}. Its source code
-can be found in {\tt frontends/verilog/parser.y} in the Yosys source tree.
+can be found in {\tt frontends/verilog/verilog\_parser.y} in the Yosys source tree.
It generates an AST using the \lstinline[language=C++]{AST::AstNode} data structure
defined in {\tt frontends/ast/ast.h}. An \lstinline[language=C++]{AST::AstNode} object has
\hline
%
{\tt AST\_PARASET} &
-Parameter set in cell instanciation \\
+Parameter set in cell instantiation \\
\hline
%
{\tt AST\_ARGUMENT} &
-Port connection in cell instanciation \\
+Port connection in cell instantiation \\
\hline
%
{\tt AST\_RANGE} &
\hline
%
{\tt AST\_CELLTYPE} &
-The type of cell in cell instanciation \\
+The type of cell in cell instantiation \\
\hline
%
{\tt AST\_IDENTIFIER} &
\hline
%
{\tt AST\_REDUCE\_BOOL} &
-Conversion from multi-bit value to boolian value
-(equivialent to {\tt AST\_REDUCE\_OR}) \\
+Conversion from multi-bit value to boolean value
+(equivalent to {\tt AST\_REDUCE\_OR}) \\
\hline
%
{\tt AST\_SHIFT\_LEFT},
\hline
%
{\tt AST\_CELL} &
-A cell instanciation \\
+A cell instantiation \\
\hline
%
{\tt AST\_PRIMITIVE} &
\hline
%
{\tt AST\_FOR} &
-A \lstinline[language=Verilog];for;-loop witn an
+A \lstinline[language=Verilog];for;-loop with an
\lstinline[language=Verilog];always;- or
\lstinline[language=Verilog];initial;-block \\
\hline
\subsection{Generating RTLIL}
After AST simplification, the \lstinline[language=C++]{AST::AstNode::genRTLIL()} method of each {\tt AST\_MODULE} node
-in the AST is called. This initiates a recursive process that generates equivialent RTLIL data for the AST data.
+in the AST is called. This initiates a recursive process that generates equivalent RTLIL data for the AST data.
The \lstinline[language=C++]{AST::AstNode::genRTLIL()} method returns an \lstinline[language=C++]{RTLIL::SigSpec} structure.
For nodes that represent expressions (operators, constants, signals, etc.), the cells needed to implement the calculation
generated \lstinline[language=C++]{RTLIL::Process}.
\end{itemize}
-As the algorithm runs these variables are continously modified as well as pushed
+As the algorithm runs these variables are continuously modified as well as pushed
to the stack and later restored to their earlier values by popping from the stack.
On startup the ProcessGenerator generates a new
\item A new \lstinline[language=C++]{RTLIL::SwitchRule} object is generated, the selection expression is evaluated using
\lstinline[language=C++]{AST::AstNode::genRTLIL()} (with the use of \lstinline[language=C++]{subst_rvalue_from} and
\lstinline[language=C++]{subst_rvalue_to}) and added to the \lstinline[language=C++]{RTLIL::SwitchRule} object and the
-obect is added to the \lstinline[language=C++]{current_case}.
+object is added to the \lstinline[language=C++]{current_case}.
%
\item All lvalues assigned to within the {\tt AST\_CASE} node using blocking assignments are collected and
saved in the local variable \lstinline[language=C++]{this_case_eq_lvalue}.
\begin{fixme}
Add some information on the generation of {\tt \$memrd} and {\tt \$memwr} cells
-and how they are processsed in the {\tt memory} pass.
+and how they are processed in the {\tt memory} pass.
\end{fixme}
\section{Synthesizing Parametric Designs}
projects / yosys.git / blobdiff