\subsubsection{Selecting by object property or type}
\begin{frame}[fragile]{\subsubsecname}
-Special pattern can be used to select by object property or type. For example:
+Special patterns can be used to select by object property or type. For example:
\bigskip
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
\subsubsection{Combining selection}
\begin{frame}[fragile]{\subsubsecname}
-When more than one selection expression is used in one statement they are
+When more than one selection expression is used in one statement, then they are
pushed on a stack. The final elements on the stack are combined into a union:
\medskip
\subsubsection{Incremental selection}
\begin{frame}[fragile]{\subsubsecname}
-Sometime a selection can most easily described by a series of add/delete operations.
+Sometimes a selection can most easily be described by a series of add/delete operations.
The commands {\tt select -add} and {\tt select -del} respectively add or remove objects
from the current selection instead of overwriting it.
\begin{itemize}
\item
The {\tt techmap} command replaces cells in the design with implementations given
-as verilog code (called ``map files''). It can replace Yosys' internal cell
+as Verilog code (called ``map files''). It can replace Yosys' internal cell
types (such as {\tt \$or}) as well as user-defined cell types.
\medskip\item
Verilog parameters are used extensively to customize the internal cell types.
\subsubsection{Intro to coarse-grain synthesis}
\begin{frame}[fragile]{\subsubsecname}
-In coarse-grain synthesis the target architecure has cells of the same
+In coarse-grain synthesis the target architecture has cells of the same
complexity or larger complexity than the internal RTL representation.
For example:
\begin{frame}{\subsubsecname}
\scriptsize
Often a coarse-grain element has a constant bit-width, but can be used to
-implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier
+implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
can also be used to implement 16x20-bit multiplication.
\bigskip
\hfil\begin{tikzpicture}
\node at (0,0) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2d.pdf}};
-\node at (0,-4) {\includegraphics[width=11cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
+\node at (0,-4) {\includegraphics[width=8cm,trim=1.5cm 1.5cm 1.5cm 1.5cm]{PRESENTATION_ExAdv/macc_xilinx_test2e.pdf}};
\node at (1,-1.7) {\begin{lstlisting}[linewidth=5.5cm, frame=single, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
techmap -map macc_xilinx_unwrap_map.v ;;
\end{lstlisting}};
\item {\bf Behavioral changes} \\
Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
-changing asynchonous resets to synchronous resets. This has applications in design space exploration
+changing asynchronous resets to synchronous resets. This has applications in design space exploration
(evaluation of various architectures for one circuit).
\end{itemize}
\end{frame}
parameter CLK_POLARITY = 1;
parameter ARST_POLARITY = 1;
parameter ARST_VALUE = 0;
-
+
input CLK, ARST;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
-
+
wire [1023:0] _TECHMAP_DO_ = "proc";
-
+
wire _TECHMAP_FAIL_ = !CLK_POLARITY || !ARST_POLARITY;
\end{lstlisting}
\vss}
\begin{frame}{\subsecname}
\begin{itemize}
-\item A lot can be achived in Yosys just with the standard set of commands.
+\item A lot can be achieved in Yosys just with the standard set of commands.
\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
\end{itemize}
projects / yosys.git / blobdiff