\begin{frame}{\subsecname}
\begin{itemize}
\item Reading and elaborating the design
-\item High-level synthesis and optimization
+\item Higher-level synthesis and optimization
\begin{itemize}
\item Converting {\tt always}-blocks to logic and registers
\item Perform coarse-grain optimizations (resource sharing, const folding, ...)
\end{itemize}
\item Convert remaining logic to bit-level logic functions
\item Perform optimizations on bit-level logic functions
-\item Map bit-level logic and register to gates from cell library
-\item Write results to output file
+\item Map bit-level logic gates and registers to cell library
+\item Write results to output file
\end{itemize}
\end{frame}
#
hierarchy
-# recommended form. fail if parts of the design hierarchy are missing. remove
-# everything that is unreachable by the top module. mark the top module.
+# recommended form. fails if parts of the design hierarchy are missing, removes
+# everything that is unreachable from the top module, and marks the top module.
#
hierarchy -check -top top_module
\end{lstlisting}
is a macro command that calls other commands:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-opt_const # const folding
-opt_share -nomux # merging identical cells
+opt_expr # const folding and simple expression rewriting
+opt_merge -nomux # merging identical cells
do
opt_muxtree # remove never-active branches from multiplexer tree
opt_reduce # consolidate trees of boolean ops to reduce functions
- opt_share # merging identical cells
+ opt_merge # merging identical cells
opt_rmdff # remove/simplify registers with constant inputs
opt_clean # remove unused objects (cells, wires) from design
- opt_const # const folding
+ opt_expr # const folding and simple expression rewriting
while [changed design]
\end{lstlisting}
can be used as shortcut for {\tt clean}. For example:
\begin{lstlisting}[xleftmargin=0.5cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
-proc; opt; memory; opt_const;; fsm;;
+proc; opt; memory; opt_expr;; fsm;;
\end{lstlisting}
\end{frame}
\begin{frame}{\subsecname}
Usually it does not hurt to call {\tt opt} after each regular command in the
synthesis script. But it increases the synthesis time, so it is favourable
-to only call {\tt opt} when an improvement can be archieved.
+to only call {\tt opt} when an improvement can be achieved.
\bigskip
The designs in {\tt yosys-bigsim} are a good playground for experimenting with
the effects of calling {\tt opt} in various places of the flow.
\bigskip
-It generally is a good idea us call {\tt opt} before inherently expensive
+It generally is a good idea to call {\tt opt} before inherently expensive
commands such as {\tt sat} or {\tt freduce}, as the possible gain is much
higher in this cases as the possible loss.
# into one multi-port memory cell.
memory_collect
-# this takes the multi-port memory cells and transforms it to address decoder
+# this takes the multi-port memory cell and transforms it to address decoder
# logic and registers. This step is skipped if "memory" is called with -nomap.
memory_map
\end{lstlisting}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 1/2}
-\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
+\vbox to 0cm{\includegraphics[width=0.7\linewidth,trim=0cm 0cm 0cm -10cm]{PRESENTATION_ExSyn/memory_01.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
\end{frame}
\begin{frame}[t, fragile]{\subsecname{} -- Example 2/2}
-\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -6cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
+\vbox to 0cm{\hfill\includegraphics[width=7.5cm,trim=0cm 0cm 0cm -5cm]{PRESENTATION_ExSyn/memory_02.pdf}\vss}
\vskip-1cm
\begin{columns}
\column[t]{5cm}
fsm_extract
fsm_opt
-opt_clean
+clean
fsm_opt
fsm_expand # if got option -expand
-opt_clean # if got option -expand
+clean # if got option -expand
fsm_opt # if got option -expand
fsm_recode # unless got option -norecode
\end{frame}
\begin{frame}{\subsecname{} -- details}
-Some details on the most importand commands from the {\tt fsm\_*} group:
+Some details on the most important commands from the {\tt fsm\_*} group:
\bigskip
The {\tt fsm\_detect} command identifies FSM state registers and marks them
\subsection{The {\tt techmap} command}
\begin{frame}[t]{\subsecname}
-\vbox to 0cm{\includegraphics[width=12cm,trim=-18cm 0cm 0cm -34cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
+\vbox to 0cm{\includegraphics[width=12cm,trim=-15cm 0cm 0cm -20cm]{PRESENTATION_ExSyn/techmap_01.pdf}\vss}
\vskip-0.8cm
The {\tt techmap} command replaces cells with implementations given as
verilog source. For example implementing a 32 bit adder using 16 bit adders:
to map all RTL cell types to a generic library of built-in logic gates and registers.
\bigskip
-\begin{block}{The build-in logic gate types are:}
-{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
+\begin{block}{The built-in logic gate types are:}
+{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_}
\end{block}
\bigskip
hierarchy -check -top cpu_top
# high-level synthesis
-proc; opt; memory -nomap;; fsm; opt
+proc; opt; fsm;; memory -nomap; opt
# substitute block rams
techmap -map map_rams.v
\begin{itemize}
\item Yosys provides commands for each phase of the synthesis.
\item Each command solves a (more or less) simple problem.
-\item Complex command are often only front-ends to simple commands.
-\item {\tt proc; opt; memory; opt; fsm; opt; techmap; opt; abc;;}
+\item Complex commands are often only front-ends to simple commands.
+\item {\tt proc; opt; fsm; opt; memory; opt; techmap; opt; abc;;}
\end{itemize}
\bigskip
projects / yosys.git / blobdiff